Abstract: The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.
Abstract: In this paper we present high performance
dynamically allocated multi-queue (DAMQ) buffer schemes for fault
tolerance systems on chip applications that require an interconnection
network. Two virtual channels shared the same buffer space. Fault
tolerant mechanisms for interconnection networks are becoming a
critical design issue for large massively parallel computers. It is also
important to high performance SoCs as the system complexity keeps
increasing rapidly. On the message switching layer, we make
improvement to boost system performance when there are faults
involved in the components communication. The proposed scheme is
when a node or a physical channel is deemed as faulty, the previous
hop node will terminate the buffer occupancy of messages destined
to the failed link. The buffer usage decisions are made at switching
layer without interactions with higher abstract layer, thus buffer
space will be released to messages destined to other healthy nodes
quickly. Therefore, the buffer space will be efficiently used in case
fault occurs at some nodes.
Abstract: This method decrease usage power (expenditure) in networks on chips (NOC). This method data coding for data transferring in order to reduces expenditure. This method uses data compression reduces the size. Expenditure calculation in NOC occurs inside of NOC based on grown models and transitive activities in entry ports. The goal of simulating is to weigh expenditure for encoding, decoding and compressing in Baseline networks and reduction of switches in this type of networks. KeywordsNetworks on chip, Compression, Encoding, Baseline networks, Banyan networks.