Abstract: This paper describes a CMOS four-quadrant
multiplier intended for use in the front-end receiver by utilizing the
square-law characteristic of the MOS transistor in the saturation
region. The circuit is based on 0.35 um CMOS technology simulated
using HSPICE software. The mixer has a third-order inter the power
consumption is 271uW from a single 1.2V power supply. One of the
features of the proposed design is using two MOS transistors
limitation to reduce the supply voltage, which leads to reduce the
power consumption. This technique provides a GHz bandwidth
response and low power consumption.
Abstract: In this paper, a double balanced radio frequency multiplier
is presented which is customized for transmitted reference
ultra wideband (UWB) receivers. The multiplier uses 90nm model
parameters and exploits compensating transistors to provide controllable
gain for a Gilbert core. After performing periodic and quasiperiodic
non linear analyses the RF mixer (multiplier) achieves a
voltage conversion gain of 16 dB and a DSB noise figure of 8.253
dB with very low power consumption. A high degree of LO to RF
isolation (in the range of -94dB), RF to IF isolation (in the range of
-95dB) and LO to IF isolation (in the range of -143dB) is expected
for this design with an input-referred IP3 point of -1.93 dBm and an
input referred 1 dB compression point of -10.67dBm. The amount of
noise at the output is 7.7 nV/√Hz when the LO input is driven by
a 10dBm signal. The mixer manifests better results when compared
with other reported multiplier circuits and its Zero-IF performance
ensures its applicability as TR-UWB multipliers.
Abstract: With the advantage of wireless network technology,
there are a variety of mobile applications which make the issue of
wireless sensor networks as a popular research area in recent years.
As the wireless sensor network nodes move arbitrarily with the
topology fast change feature, mobile nodes are often confronted with
the void issue which will initiate packet losing, retransmitting,
rerouting, additional transmission cost and power consumption.
When transmitting packets, we would not predict void problem
occurring in advance. Thus, how to improve geographic routing with
void avoidance in wireless networks becomes an important issue. In
this paper, we proposed a greedy geographical void routing algorithm
to solve the void problem for wireless sensor networks. We use the
information of source node and void area to draw two tangents to
form a fan range of the existence void which can announce voidavoiding
message. Then we use source and destination nodes to draw
a line with an angle of the fan range to select the next forwarding
neighbor node for routing. In a dynamic wireless sensor network
environment, the proposed greedy void avoiding algorithm can be
more time-saving and more efficient to forward packets, and improve
current geographical void problem of wireless sensor networks.
Abstract: Link reliability and transmitted power are two important design constraints in wireless network design. Error control coding (ECC) is a classic approach used to increase link reliability and to lower the required transmitted power. It provides coding gain, resulting in transmitter energy savings at the cost of added decoder power consumption. But the choice of ECC is very critical in the case of wireless sensor network (WSN). Since the WSNs are energy constraint in nature, both the BER and power consumption has to be taken into count. This paper develops a step by step approach in finding suitable error control codes for WSNs. Several simulations are taken considering different error control codes and the result shows that the RS(31,21) fits both in BER and power consumption criteria.
Abstract: This paper presents a methodology towards the emulation of the electrical power consumption of the RF device during the cellular phone/handset transmission mode using the LTE technology. The emulation methodology takes the physical environmental variables and the logical interface between the baseband and the RF system as inputs to compute the emulated power dissipation of the RF device. The emulated power, in between the measured points corresponding to the discrete values of the logical interface parameters is computed as a polynomial interpolation using polynomial basis functions. The evaluation of polynomial and spline curve fitting models showed a respective divergence (test error) of 8% and 0.02% from the physically measured power consumption. The precisions of the instruments used for the physical measurements have been modeled as intervals. We have been able to model the power consumption of the RF device operating at 5MHz using homotopy between 2 continuous power consumptions of the RF device operating at the bandwidths 3MHz and 10MHz.
Abstract: A 2.4GHz (RF) down conversion Gilbert Cell mixer,
implemented in a 0.18-μm CMOS technology with a 1.8V supply, is
presented. Current bleeding (charge injection) technique has been
used to increase the conversion gain and the linearity of the mixer.
The proposed mixer provides 10.75 dB conversion gain ( C G ) with
14.3mw total power consumption. The IIP3 and 1-dB compression
point of the mixer are 8dbm and -4.6dbm respectively, at 300 MHz
IF frequencies. Comparing the current design against the
conventional mixer design, demonstrates better performance in the
conversion gain, linearity, noise figure and port-to-port isolation.
Abstract: Modeling of the dynamic behavior and motion are
renewed interest in the improved tractive performance of an
intelligent air-cushion tracked vehicle (IACTV). This paper presents
a new dynamical model for the forces on the developed small scale
intelligent air-cushion tracked vehicle moving over swamp peat. The
air cushion system partially supports the 25 % of vehicle total weight
in order to make the vehicle ground contact pressure 7 kN/m2. As the
air-cushion support system can adjust automatically on the terrain, so
the vehicle can move over the terrain without any risks. The springdamper
system is used with the vehicle body to control the aircushion
support system on any undulating terrain by making the
system sinusoidal form. Experiments have been carried out to
investigate the relationships among tractive efficiency, slippage,
traction coefficient, load distribution ratio, tractive effort, motion
resistance and power consumption in given terrain conditions.
Experiment and simulation results show that air-cushion system
improves the vehicle performance by keeping traction coefficient of
71% and tractive efficiency of 62% and the developed model can
meet the demand of transport efficiency with the optimal power
consumption.
Abstract: In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.
Abstract: Versatile dual-mode class-AB CMOS four-quadrant
analog multiplier circuit is presented. The dual translinear loops and
current mirrors are the basic building blocks in realization scheme.
This technique provides; wide dynamic range, wide-bandwidth response
and low power consumption. The major advantages of this
approach are; its has single ended inputs; since its input is dual translinear
loop operate in class-AB mode which make this multiplier
configuration interesting for low-power applications; current multiplying,
voltage multiplying, or current and voltage multiplying can
be obtainable with balanced input. The simulation results of versatile
analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth
of about 19MHz, a maximum power consumption of 0.46mW,
and temperature compensated. Operation of versatile analog multiplier
was also confirmed through an experiment using CMOS transistor
array.