Abstract: Efficient modulo 2n+1 adders are important for
several applications including residue number system, digital signal
processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented
number system. The proposed approach is introduced for the
reduction of the power dissipated. In a conventional modulo 2n+1
adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit
circuits, the diminished-1 and carry save diminished-1 number
systems can be effectively used in applications. In the paper, we also
derive two new architectures for designing modulo 2n+1 adder, based
on n-bit ripple-carry adder. The first architecture is a faster design
whereas the second one uses less hardware. In the proposed method,
the special treatment required for zero operands in Diminished-1
number system is removed. In the fastest modulo 2n+1 adders in
normal binary system, there are 3-operand adders. This problem is
also resolved in this paper. The proposed architectures are compared
with some efficient adders based on ripple-carry adder and highspeed
adder. It is shown that the hardware overhead and power
consumption will be reduced. As well as power reduction, in some
cases, power-delay product will be also reduced.
Abstract: In this report, an OTA which is used in fully
differential pipelined ADC was described. Using gain-boost
architecture with difference-ended amplifier, this OTA achieve
high-gain and high-speed. Besides, the CMFB circuit is also used, and
some methods are concerned to improve the performance. Then, by
optimization the layout design, OTA-s mismatch was reduced. This
design was using TSMC 0.18um CMOS process and simulation both
schematic and layout in Cadence. The result of the simulation shows
that the OTA has a gain up to 80dB,a unity gain bandwidth of about
1.437GHz for a 2pF load, a slew rate is about 428V/μs, a output swing
is 0.2V~1.35V, with the power supply of 1.8V, the power
consumption is 88mW. This amplifier was used in a 10bit 150MHz
pipelined ADC.
Abstract: Design Patterns have gained more and more
acceptances since their emerging in software development world last
decade and become another de facto standard of essential knowledge
for Object-Oriented Programming developers nowadays.
Their target usage, from the beginning, was for regular computers,
so, minimizing power consumption had never been a concern.
However, in this decade, demands of more complicated software for
running on mobile devices has grown rapidly as the much higher
performance portable gadgets have been supplied to the market
continuously. To get along with time to market that is business
reason, the section of software development for power conscious,
battery, devices has shifted itself from using specific low-level
languages to higher level ones. Currently, complicated software
running on mobile devices are often developed by high level
languages those support OOP concepts. These cause the trend of
embracing Design Patterns to mobile world.
However, using Design Patterns directly in software development
for power conscious systems is not recommended because they were
not originally designed for such environment. This paper
demonstrates the adapted Design Pattern for power limitation system.
Because there are numerous original design patterns, it is not possible
to mention the whole at once. So, this paper focuses only in creating
Energy Conscious version of existing regular "Builder Pattern" to be
appropriated for developing low power consumption software.
Abstract: 98% of the energy needed in Taiwan has been
imported. The prices of petroleum and electricity have been
increasing. In addition, facility capacity, amount of electricity
generation, amount of electricity consumption and number of Taiwan
Power Company customers have continued to increase. For these
reasons energy conservation has become an important topic. In the
past linear regression was used to establish the power consumption
models for chillers. In this study, grey prediction is used to evaluate
the power consumption of a chiller so as to lower the total power
consumption at peak-load (so that the relevant power providers do not
need to keep on increasing their power generation capacity and facility
capacity).
In grey prediction, only several numerical values (at least four
numerical values) are needed to establish the power consumption
models for chillers. If PLR, the temperatures of supply chilled-water
and return chilled-water, and the temperatures of supply cooling-water
and return cooling-water are taken into consideration, quite accurate
results (with the accuracy close to 99% for short-term predictions)
may be obtained. Through such methods, we can predict whether the
power consumption at peak-load will exceed the contract power
capacity signed by the corresponding entity and Taiwan Power
Company. If the power consumption at peak-load exceeds the power
demand, the temperature of the supply chilled-water may be adjusted
so as to reduce the PLR and hence lower the power consumption.
Abstract: In recent years there has been renewal of interest in the
relation between Green IT and Cloud Computing. The growing use of
computers in cloud platform has caused marked energy consumption,
putting negative pressure on electricity cost of cloud data center. This
paper proposes an effective mechanism to reduce energy utilization in
cloud computing environments. We present initial work on the
integration of resource and power management that aims at reducing
power consumption. Our mechanism relies on recalling virtualization
services dynamically according to user-s virtualization request and
temporarily shutting down the physical machines after finish in order
to conserve energy. Given the estimated energy consumption, this
proposed effort has the potential to positively impact power
consumption. The results from the experiment concluded that energy
indeed can be saved by powering off the idling physical machines in
cloud platforms.
Abstract: This paper describes a CMOS four-quadrant
multiplier intended for use in the front-end receiver by utilizing the
square-law characteristic of the MOS transistor in the saturation
region. The circuit is based on 0.35 um CMOS technology simulated
using HSPICE software. The mixer has a third-order inter the power
consumption is 271uW from a single 1.2V power supply. One of the
features of the proposed design is using two MOS transistors
limitation to reduce the supply voltage, which leads to reduce the
power consumption. This technique provides a GHz bandwidth
response and low power consumption.
Abstract: In first stage of each microwave receiver there is Low
Noise Amplifier (LNA) circuit, and this stage has important rule in
quality factor of the receiver. The design of a LNA in Radio
Frequency (RF) circuit requires the trade-off many importance
characteristics such as gain, Noise Figure (NF), stability, power
consumption and complexity. This situation Forces desingners to
make choices in the desing of RF circuits. In this paper the aim is to
design and simulate a single stage LNA circuit with high gain and
low noise using MESFET for frequency range of 5 GHz to 6 GHz.
The desing simulation process is down using Advance Design
System (ADS). A single stage LNA has successfully designed with
15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3
GHz. Also the designed LNA should be working stably In a
frequency range of 5 GHz to 6 GHz.
Abstract: This article presents a current-mode quadrature
oscillator using differential different current conveyor (DDCC) and
voltage differencing transconductance amplifier (VDTA) as active
elements. The proposed circuit is realized fro m a non-inverting
lossless integrator and an inverting second order low-pass filter. The
oscillation condition and oscillation frequency can be
electronically/orthogonally controlled via input bias currents. The
circuit description is very simple, consisting of merely 1 DDCC, 1
VDTA, 1 grounded resistor and 3 grounded capacitors. Using only
grounded elements, the proposed circuit is then suitable for IC
architecture. The proposed oscillator has high output impedance
which is easy to cascade or dive the external load without the buffer
devices. The PSPICE simulation results are depicted, and the given
results agree well with the theoretical anticipation. The power
consumption is approximately 1.76mW at ±1.25V supply voltages.