Abstract: Radio Frequency Identification (RFID) is a blooming technology which uses radio frequency to track the objects. This technology transmits signals between tag and reader to fetch information from the tag with a unique serial identity. Generally, the drawbacks of RFID technology are high cost, high consumption of power and weak authentication systems between a reader and a tag. The proposed protocol utilizes less dynamic power using reversible truncated multipliers which are implemented in RFID tag-reader with mutual authentication protocol system to reduce both leakage and dynamic power consumption. The proposed system was simulated using Xilinx and Cadence tools.
Abstract: Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.
Abstract: Nowadays, demand for using real-time video transmission capable devices is ever-increasing. So, high resolution videos have made efficient video compression techniques an essential component for capturing and transmitting video data. Motion estimation has a critical role in encoding raw video. Hence, various motion estimation methods are introduced to efficiently compress the video. Low bit‑depth representation based motion estimation methods facilitate computation of matching criteria and thus, provide small hardware footprint. In this paper, a hardware implementation of a two-bit transformation based low-complexity motion estimation method using local binary pattern approach is proposed. Image frames are represented in two-bit depth instead of full-depth by making use of the local binary pattern as a binarization approach and the binarization part of the hardware architecture is explained in detail. Experimental results demonstrate the difference between the proposed hardware architecture and the architectures of well-known low-complexity motion estimation methods in terms of important aspects such as resource utilization, energy and power consumption.
Abstract: The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.
Abstract: Reversible logic as a new favorable design domain can be used for various fields especially creating quantum computers because of its speed and intangible power consumption. However, its susceptibility to a variety of environmental effects may lead to yield the incorrect results. In this paper, because of the importance of multiplication operation in various computing systems, some novel reversible logic array multipliers are proposed with error detection capability by incorporating the parity-preserving gates. The new designs are presented for two main parts of array multipliers, partial product generation and multi-operand addition, by exploiting the new arrangements of existing gates, which results in two signed parity-preserving array multipliers. The experimental results reveal that the best proposed 4×4 multiplier in this paper reaches 12%, 24%, and 26% enhancements in the number of constant inputs, number of required gates, and quantum cost, respectively, compared to previous design. Moreover, the best proposed design is generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.
Abstract: In this paper, firstly, we present the mathematical modeling of finite impulse response (FIR) filter and Cascaded Integrator Comb (CIC) filter for sampling rate reduction and then an extension of Canonical signed digit (CSD) based efficient structure is presented in framework using hybrid signed digit (HSD) arithmetic. CSD representation imposed a restriction that two non-zero CSD coefficient bits cannot acquire adjacent bit positions and therefore, represented structure is not economical in terms of speed, area and power consumption. The HSD based structure gives optimum performance in terms of area and speed with 37.02% passband droop compensation.
Abstract: This paper deals with a mini radar system aimed at detecting small targets at the low latitude. The radar operates at Ku-band in the frequency modulated continuous wave (FMCW) mode with two receiving channels. The radar system has the characteristics of compactness, mobility, and low power consumption. This paper focuses on the implementation of the radar system, and the Block least mean square (Block LMS) algorithm is applied to minimize the fortuitous distortion. It is validated from a series of experiments that the track of the unmanned aerial vehicle (UAV) can be easily distinguished with the radar system.
Abstract: Dielectric barrier discharge plasma actuators (DBD-PAs) have been developed for active flow control devices. However, it is necessary to reduce ozone produced by DBD toward practical applications using DBD-PAs. In this study, variations of ozone concentration, flow velocity, power consumption were investigated by changing exposed electrodes of DBD-PAs. Two exposed electrode prototypes were prepared: span-type with exposed electrode width of 0.1 mm, and normal-type with width of 5 mm. It was found that span-type shows lower power consumption and higher flow velocity than that of normal-type at Vp-p = 4.0-6.0 kV. Ozone concentration of span-type higher than normal-type at Vp-p = 4.0-8.0 kV. In addition, it was confirmed that catalyst located in downstream from the exposed electrode can reduce ozone concentration between 18 and 42% without affecting the induced flow.
Abstract: Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.
Abstract: This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.
Abstract: In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.
Abstract: Wireless sensor networks (WSNs), are constantly in demand to process information more rapidly with less energy and area cost. Presently, processor based solutions have difficult to achieve high processing speed with low-power consumption. This paper presents a simple and accurate data processing scheme for low power wireless sensor node, based on reduced number of processing element (PE). The presented model provides a simple recursive structure (SRS) to process the sampled data in the wireless sensor environment and to reduce the power consumption in wireless sensor node. Based on this model, to process the incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. The ModelSim simulator used to simulate SRS structure. Functional simulation is carried out for the validation of the presented architecture. Xilinx Power Estimator (XPE) tool is used to measure the power consumption. The experimental results show the average power consumption of 91 mW; this is 42% improvement compared to the folded tree architecture.
Abstract: In a conventional network, most network devices, such as routers, are dedicated devices that do not have much variation in capacity. In recent years, a new concept of network functions virtualisation (NFV) has come into use. The intention is to implement a variety of network functions with software on general-purpose servers and this allows the network operator to select their capacities and locations without any constraints. This paper focuses on the allocation of NFV-based routing functions which are one of critical network functions, and presents the virtual routing function allocation algorithm that minimizes the total power consumption. In addition, this study presents the useful allocation policy of virtual routing functions, based on an evaluation with a ladder-shaped network model. This policy takes the ratio of the power consumption of a routing function to that of a circuit and traffic distribution between areas into consideration. Furthermore, the present paper shows that there are cases where the use of NFV-based routing functions makes it possible to reduce the total power consumption dramatically, in comparison to a conventional network, in which it is not economically viable to distribute small-capacity routing functions.
Abstract: Ubiquity of natural disasters during last few decades
have risen serious questions towards the prediction of such events
and human safety. Every disaster regardless its proportion has a
precursor which is manifested as a disruption of some environmental
parameter such as temperature, humidity, pressure, vibrations and
etc. In order to anticipate and monitor those changes, in this paper
we propose an overall system for disaster prediction and monitoring,
based on wireless sensor network (WSN). Furthermore, we introduce
a modified and simplified WSN routing protocol built on the top
of the trickle routing algorithm. Routing algorithm was deployed
using the bluetooth low energy protocol in order to achieve low
power consumption. Performance of the WSN network was analyzed
using a real life system implementation. Estimates of the WSN
parameters such as battery life time, network size and packet delay are
determined. Based on the performance of the WSN network, proposed
system can be utilized for disaster monitoring and prediction due to
its low power profile and mesh routing feature.
Abstract: An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.
Abstract: Interaction between mixing and crystallization is often
ignored despite the fact that it affects almost every aspect of the
operation including nucleation, growth, and maintenance of the
crystal slurry. This is especially pronounced in multiple impeller
systems where flow complexity is increased. By choosing proper
mixing parameters, what closely depends on the knowledge of the
hydrodynamics in a mixing vessel, the process of batch cooling
crystallization may considerably be improved. The values that render
useful information when making this choice are mixing time and
power consumption. The predominant motivation for this work was
to investigate the extent to which radial dual impeller configuration
influences mixing time, power consumption and consequently the
values of metastable zone width and nucleation rate. In this research,
crystallization of borax was conducted in a 15 dm3 baffled batch
cooling crystallizer with an aspect ratio (H/T) of 1.3. Mixing was
performed using two straight blade turbines (4-SBT) mounted on the
same shaft that generated radial fluid flow. Experiments were
conducted at different values of N/NJS ratio (impeller speed/
minimum impeller speed for complete suspension), D/T ratio
(impeller diameter/crystallizer diameter), c/D ratio (lower impeller
off-bottom clearance/impeller diameter), and s/D ratio (spacing
between impellers/impeller diameter). Mother liquor was saturated at
30°C and was cooled at the rate of 6°C/h. Its concentration was
monitored in line by Na-ion selective electrode. From the values of
supersaturation that was monitored continuously over process time, it
was possible to determine the metastable zone width and
subsequently the nucleation rate using the Mersmann’s nucleation
criterion. For all applied dual impeller configurations, the mixing
time was determined by potentiometric method using a pulse
technique, while the power consumption was determined using a
torque meter produced by Himmelstein & Co. Results obtained in
this investigation show that dual impeller configuration significantly
influences the values of mixing time, power consumption as well as
the metastable zone width and nucleation rate. A special attention
should be addressed to the impeller spacing considering the flow
interaction that could be more or less pronounced depending on the
spacing value.
Abstract: Many cluster based routing protocols have been
proposed in the field of wireless sensor networks, in which a group of
nodes are formed as clusters. A cluster head is selected from one
among those nodes based on residual energy, coverage area, number
of hops and that cluster-head will perform data gathering from
various sensor nodes and forwards aggregated data to the base station
or to a relay node (another cluster-head), which will forward the
packet along with its own data packet to the base station. Here a
Game Theory based Diligent Energy Utilization Algorithm (GTDEA)
for routing is proposed. In GTDEA, the cluster head selection is done
with the help of game theory, a decision making process, that selects
a cluster-head based on three parameters such as residual energy
(RE), Received Signal Strength Index (RSSI) and Packet Reception
Rate (PRR). Finding a feasible path to the destination with minimum
utilization of available energy improves the network lifetime and is
achieved by the proposed approach. In GTDEA, the packets are
forwarded to the base station using inter-cluster routing technique,
which will further forward it to the base station. Simulation results
reveal that GTDEA improves the network performance in terms of
throughput, lifetime, and power consumption.
Abstract: Maintaining factory default battery endurance rate
over time in supporting huge amount of running applications on
energy-restricted mobile devices has created a new challenge for
mobile applications developer. While delivering customers’
unlimited expectations, developers are barely aware of efficient use
of energy from the application itself. Thus, developers need a set of
valid energy consumption indicators in assisting them to develop
energy saving applications. In this paper, we present a few software
product metrics that can be used as an indicator to measure energy
consumption of Android-based mobile applications in the early of
design stage. In particular, Trepn Profiler (Power profiling tool for
Qualcomm processor) has used to collect the data of mobile
application power consumption, and then analyzed for the 23
software metrics in this preliminary study. The results show that
McCabe cyclomatic complexity, number of parameters, nested block
depth, number of methods, weighted methods per class, number of
classes, total lines of code and method lines have direct relationship
with power consumption of mobile application.
Abstract: The main issue in designing a wireless sensor network
(WSN) is the finding of a proper routing protocol that complies with
the several requirements of high reliability, short latency, scalability,
low power consumption, and many others. This paper proposes a
novel routing algorithm that complies with these design
requirements. The new routing protocol divides the WSN into several subnetworks
and each sub-network is divided into several clusters. This
division is designed to reduce the number of radio transmission and
hence decreases the power consumption. The network division may
be changed dynamically to adapt with the network changes and
allows the realization of the design requirements.
Abstract: The paper presents actual benefits and drawbacks of a multidirectional autonomous hovercraft conceived with limited resources and designed for indoor exploration. Recent developments in the field have led to the apparition of very powerful automotive systems capable of very high calculation and exploration in complex unknown environments. They usually propose very complex algorithms, high precision/cost sensors and sometimes have heavy calculation consumption with complex data fusion. These systems are usually powerful but have a certain price, and the benefits may not be worth the cost, especially considering their hardware limitations and their power consumption. The present approach is to build a compromise between cost, power consumption and results preciseness.