Abstract: Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Abstract: This paper aims to present the design, fabrication and test of a novel piezoelectric actuated, check-valves embedded micropump having the advantages of miniature size, light weight and low power consumption. This device is designed to pump gases and liquids with the capability of performing the self-priming and bubble-tolerant work mode by maximizing the stroke volume of the membrane as well as the compression ratio via minimization of the dead volume of the micropump chamber and channel. By experiment apparatus setup, we can get the real-time values of the flow rate of micropump, the displacement of the piezoelectric actuator and the deformation of the check valve, simultaneously. The micropump with check valve 0.4 mm in thickness obtained higher output performance under the sinusoidal waveform of 120 Vpp. The micropump achieved the maximum pumping rates of 42.2 ml/min and back pressure of 14.0 kPa at the corresponding frequency of 28 and 20 Hz. The presented micropump is able to pump gases with a pumping rate of 196 ml/min at operating frequencies of 280 Hz under the sinusoidal waveform of 120 Vpp.
Abstract: A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.
Abstract: This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.
Abstract: Mostly the systems are dealing with time varying
signals. The Power efficiency can be achieved by adapting the system
activity according to the input signal variations. In this context
an adaptive rate filtering technique, based on the level crossing sampling
is devised. It adapts the sampling frequency and the filter order
by following the input signal local variations. Thus, it correlates the
processing activity with the signal variations. Interpolation is required
in the proposed technique. A drastic reduction in the interpolation
error is achieved by employing the symmetry during the interpolation
process. Processing error of the proposed technique is
calculated. The computational complexity of the proposed filtering
technique is deduced and compared to the classical one. Results
promise a significant gain of the computational efficiency and hence
of the power consumption.
Abstract: This paper presents a synthetic jet air blower actuated
by PZT for air blowing for air-breathing micro PEM fuel cell. The
several factors to affect the performance of air-breathing PEM fuel cell
such as air flow rate, opening ratio and cathode open type in the
cathode side were studied. Especially, an air flow rate is critical
condition to improve its performance. In this paper, we developed a
synthetic jet air blower to supply a high stoichiometric air flow. The
synthetic jet mechanism is a zero mass flux device that converts
electrical energy into the momentum. The synthetic jet actuation is
usually generated by a traditional PZT actuator, which consists of a
small cylindrical cavity, in/outlet channel and PZT diaphragms. The
flow rate of the fabricated synthetic jet air blower was 400cc/min at
550Hz and its power consumption was very low under 0.3W. The
proposed air-breathing PEM fuel cell which installed synthetic jet air
blower was higher performance and stability during continuous
operation than the air-breathing fuel cell without auxiliary device to
supply the air. The results showed that the maximum power density
was 188mW/cm2 at 400mA/cm2. This maximum power density and
durability were improved more than 40% and 20%, respectively.
Abstract: Low power consumption is a major constraint for battery-powered system like computer notebook or PDA. In the past, specialists usually designed both specific optimized equipments and codes to relief this concern. Doing like this could work for quite a long time, however, in this era, there is another significant restraint, the time to market. To be able to serve along the power constraint while can launch products in shorter production period, objectoriented programming (OOP) has stepped in to this field. Though everyone knows that OOP has quite much more overhead than assembly and procedural languages, development trend still heads to this new world, which contradicts with the target of low power consumption. Most of the prior power related software researches reported that OOP consumed much resource, however, as industry had to accept it due to business reasons, up to now, no papers yet had mentioned about how to choose the best OOP practice in this power limited boundary. This article is the pioneer that tries to specify and propose the optimized strategy in writing OOP software under energy concerned environment, based on quantitative real results. The language chosen for studying is C# based on .NET Framework 2.0 which is one of the trendy OOP development environments. The recommendation gotten from this research would be a good roadmap that can help developers in coding that well balances between time to market and time of battery.
Abstract: In this paper we present a full performance analysis of an energy conserving routing protocol in mobile ad hoc network, named ER-AODV (Energy Reverse Ad-hoc On-demand Distance Vector routing). ER-AODV is a reactive routing protocol based on a policy which combines two mechanisms used in the basic AODV protocol. AODV and most of the on demand ad hoc routing protocols use single route reply along reverse path. Rapid change of topology causes that the route reply could not arrive to the source node, i.e. after a source node sends several route request messages, the node obtains a reply message, and this increases in power consumption. To avoid these problems, we propose a mechanism which tries multiple route replies. The second mechanism proposes a new adaptive approach which seeks to incorporate the metric "residual energy " in the process route selection, Indeed the residual energy of mobile nodes were considered when making routing decisions. The results of simulation show that protocol ER-AODV answers a better energy conservation.
Abstract: Active vibration isolation systems are less commonly
used than passive systems due to their associated cost and power
requirements. In principle, semi-active isolation systems can deliver
the versatility, adaptability and higher performance of fully active
systems for a fraction of the power consumption. Various semi-active
control algorithms have been suggested in the past. This paper
studies the 4DOF model of semi-active suspension performance
controlled by on–off and continuous skyhook damping control
strategy. The frequency and transient responses of model are
evaluated in terms of body acceleration, roll angle and tire deflection
and are compared with that of a passive damper. The results show
that the semi-active system controlled by skyhook strategy always
provides better isolation than a conventional passively damped
system except at tire natural frequencies.
Abstract: Although White LED lighting systems powered by solar cells have presented for many years, they are not widely used in today application because of their cost and low energy conversion efficiency. The proposed system use the dc power generated by fixed solar cells module to energize White LED light sources that are operated by directly connected White LED with current limitation resistors, resulting in much more power consumption. This paper presents the use of white LED as a general lighting application powered by tracking solar cells module and using pulse to apply the electrical power to the White LED. These systems resulted in high efficiency power conversion, low power consumption, and long light of the white LED.
Abstract: WOLED is widely used as lighting for high efficacy and little power consumption. In this research, power factor testing between WOLED and fluorescent lamp to see which one is more efficient in consuming energy. Since both lamps use semiconductor components, so calculation of the power factor need to consider the effects of harmonics. Harmonic make bigger losses. The study is conducted by comparing the value of the power factor regardless of harmonics (DPF) and also by included the harmonics (TPF). The average value of DPF of fluorescent is 0.953 while WOLED is 0.972. The average value of TPF of fluorescent is 0.717 whereas WOLED is 0.933. So from the review of power factor WOLED is more energy efficient than fluorescent lamp.
Abstract: In this paper the authors propose a protocol, which uses Elliptic Curve Cryptography (ECC) based on the ElGamal-s algorithm, for sending small amounts of data via an authentication server. The innovation of this approach is that there is no need for a symmetric algorithm or a safe communication channel such as SSL. The reason that ECC has been chosen instead of RSA is that it provides a methodology for obtaining high-speed implementations of authentication protocols and encrypted mail techniques while using fewer bits for the keys. This means that ECC systems require smaller chip size and less power consumption. The proposed protocol has been implemented in Java to analyse its features and vulnerabilities in the real world.
Abstract: 98% of the energy needed in Taiwan has been
imported. The prices of petroleum and electricity have been
increasing. In addition, facility capacity, amount of electricity
generation, amount of electricity consumption and number of Taiwan
Power Company customers have continued to increase. For these
reasons energy conservation has become an important topic. In the
past linear regression was used to establish the power consumption
models for chillers. In this study, grey prediction is used to evaluate
the power consumption of a chiller so as to lower the total power
consumption at peak-load (so that the relevant power providers do not
need to keep on increasing their power generation capacity and facility
capacity).
In grey prediction, only several numerical values (at least four
numerical values) are needed to establish the power consumption
models for chillers. If PLR, the temperatures of supply chilled-water
and return chilled-water, and the temperatures of supply cooling-water
and return cooling-water are taken into consideration, quite accurate
results (with the accuracy close to 99% for short-term predictions)
may be obtained. Through such methods, we can predict whether the
power consumption at peak-load will exceed the contract power
capacity signed by the corresponding entity and Taiwan Power
Company. If the power consumption at peak-load exceeds the power
demand, the temperature of the supply chilled-water may be adjusted
so as to reduce the PLR and hence lower the power consumption.
Abstract: Power consumption of nodes in ad hoc networks is a
critical issue as they predominantly operate on batteries. In order to
improve the lifetime of an ad hoc network, all the nodes must be
utilized evenly and the power required for connections must be
minimized. In this project a link layer algorithm known as Power
Aware medium Access Control (PAMAC) protocol is proposed
which enables the network layer to select a route with minimum total
power requirement among the possible routes between a source and a
destination provided all nodes in the routes have battery capacity
above a threshold. When the battery capacity goes below a
predefined threshold, routes going through these nodes will be
avoided and these nodes will act only as source and destination.
Further, the first few nodes whose battery power drained to the set
threshold value are pushed to the exterior part of the network and the
nodes in the exterior are brought to the interior. Since less total
power is required to forward packets for each connection. The
network layer protocol AOMDV is basically an extension to the
AODV routing protocol. AOMDV is designed to form multiple
routes to the destination and it also avoid the loop formation so that it
reduces the unnecessary congestion to the channel. In this project, the
performance of AOMDV is evaluated using PAMAC as a MAC layer
protocol and the average power consumption, throughput and
average end to end delay of the network are calculated and the results
are compared with that of the other network layer protocol AODV.
Abstract: Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m2 . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.
Abstract: A new low-voltage floating gate MOSFET (FGMOS)
based squarer using square law characteristic of the FGMOS is
proposed in this paper. The major advantages of the squarer are simplicity,
rail-to-rail input dynamic range, low total harmonic distortion,
and low power consumption. The proposed circuit is biased without
body effect. The circuit is designed and simulated using SPICE in
0.25μm CMOS technology. The squarer is operated at the supply
voltages of ±0.75V . The total harmonic distortion (THD) for the
input signal 0.75Vpp at 25 KHz, and maximum power consumption
were found to be less than 1% and 319μW respectively.
Abstract: In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.
Abstract: with increasing circuits- complexity and demand to
use portable devices, power consumption is one of the most
important parameters these days. Full adders are the basic block of
many circuits. Therefore reducing power consumption in full adders
is very important in low power circuits. One of the most powerconsuming
modules in full adders is XOR/XNOR circuit. This paper
presents two new full adders based on two new logic approaches. The
proposed logic approaches use one XOR or XNOR gate to implement
a full adder cell. Therefore, delay and power will be decreased. Using
two new approaches and two XOR and XNOR gates, two new full
adders have been implemented in this paper. Simulations are carried
out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage.
The results show that the ten-transistors proposed full adder has 12%
less power consumption and is 5% faster in comparison to MB12T
full adder. 9T is more efficient in area and is 24% better than similar
10T full adder in term of power consumption. The main drawback of
the proposed circuits is output threshold loss problem.
Abstract: In Image processing the Image compression can improve
the performance of the digital systems by reducing the cost and
time in image storage and transmission without significant reduction
of the Image quality. This paper describes hardware architecture of
low complexity Discrete Cosine Transform (DCT) architecture for
image compression[6]. In this DCT architecture, common computations
are identified and shared to remove redundant computations
in DCT matrix operation. Vector processing is a method used for
implementation of DCT. This reduction in computational complexity
of 2D DCT reduces power consumption. The 2D DCT is performed
on 8x8 matrix using two 1-Dimensional Discrete cosine transform
blocks and a transposition memory [7]. Inverse discrete cosine
transform (IDCT) is performed to obtain the image matrix and
reconstruct the original image. The proposed image compression
algorithm is comprehended using MATLAB code. The VLSI design
of the architecture is implemented Using Verilog HDL. The proposed
hardware architecture for image compression employing DCT was
synthesized using RTL complier and it was mapped using 180nm
standard cells. . The Simulation is done using Modelsim. The
simulation results from MATLAB and Verilog HDL are compared.
Detailed analysis for power and area was done using RTL compiler
from CADENCE. Power consumption of DCT core is reduced to
1.027mW with minimum area[1].
Abstract: In recent years there has been renewal of interest in the
relation between Green IT and Cloud Computing. The growing use of
computers in cloud platform has caused marked energy consumption,
putting negative pressure on electricity cost of cloud data center. This
paper proposes an effective mechanism to reduce energy utilization in
cloud computing environments. We present initial work on the
integration of resource and power management that aims at reducing
power consumption. Our mechanism relies on recalling virtualization
services dynamically according to user-s virtualization request and
temporarily shutting down the physical machines after finish in order
to conserve energy. Given the estimated energy consumption, this
proposed effort has the potential to positively impact power
consumption. The results from the experiment concluded that energy
indeed can be saved by powering off the idling physical machines in
cloud platforms.