Abstract: This document details the process of developing a
wireless device that captures the basic movements of the foot (plantar
flexion, dorsal flexion, abduction, adduction.), and the knee
movement (flexion). It implements a motion capture system by using
a hardware based on optical fiber sensors, due to the advantages in
terms of scope, noise immunity and speed of data transmission and
reception. The operating principle used by this system is the detection
and transmission of joint movement by mechanical elements and
their respective measurement by optical ones (in this case infrared).
Likewise, Visual Basic software is used for reception, analysis and
signal processing of data acquired by the device, generating a 3D
graphical representation in real time of each movement. The result is
a boot in charge of capturing the movement, a transmission module
(Implementing Xbee Technology) and a receiver module for
receiving information and sending it to the PC for their respective
processing.
The main idea with this device is to help on topics such as
bioengineering and medicine, by helping to improve the quality of
life and movement analysis.
Abstract: The practical implementation of audio-video coupled speech recognition systems is mainly limited by the hardware complexity to integrate two radically different information capturing devices with good temporal synchronisation. In this paper, we propose a solution based on a smart CMOS image sensor in order to simplify the hardware integration difficulties. By using on-chip image processing, this smart sensor can calculate in real time the X/Y projections of the captured image. This on-chip projection reduces considerably the volume of the output data. This data-volume reduction permits a transmission of the condensed visual information via the same audio channel by using a stereophonic input available on most of the standard computation devices such as PC, PDA and mobile phones. A prototype called VMIKE (Visio-Microphone) has been designed and realised by using standard 0.35um CMOS technology. A preliminary experiment gives encouraged results. Its efficiency will be further investigated in a large variety of applications such as biometrics, speech recognition in noisy environments, and vocal control for military or disabled persons, etc.
Abstract: This paper describes design of a digital feedback loop
for a low switching frequency dc-dc switching converters. Low
switching frequencies were selected in this design. A look up table
for the digital PID (proportional integrator differentiator)
compensator was implemented using Altera Stratix II with built-in
ADC (analog-to-digital converter) to achieve this hardware
realization. Design guidelines are given for the PID compensator,
high frequency DPWM (digital pulse width modulator) and moving
average filter.
Abstract: The need to implement intelligent highways is much
more emphasized with the growth of vehicle production line as well as vehicle intelligence. The control of intelligent vehicles in order to
reduce human error and boost ease congestion is not accomplished solely by the aid of human resources. The present article is an attempt
to introduce an intelligent control system based on a single central computer. In this project, central computer, without utilizing Global
Positioning System (GPS), is capable of tracking all vehicles, crisis management and control, traffic guidance and recording traffic
crimes along the highway. By the help of RFID technology, vehicles
are connected to computerized systems, intelligent light poles and
other available hardware along the way. By the aid of Wimax
communicative technology, all components of the system are
virtually connected together through local and global networks
devised in them and the energy of the network is provided by the
solar cells installed on the intelligent light poles.
Abstract: In this paper, RSA encryption algorithm and its hardware
implementation in Xilinx-s Virtex Field Programmable Gate
Arrays (FPGA) is analyzed. The issues of scalability, flexible performance,
and silicon efficiency for the hardware acceleration of
public key crypto systems are being explored in the present work.
Using techniques based on the interleaved math for exponentiation,
the proposed RSA calculation architecture is compared to existing
FPGA-based solutions for speed, FPGA utilization, and scalability.
The paper covers the RSA encryption algorithm, interleaved multiplication,
Miller Rabin algorithm for primality test, extended Euclidean
math, basic FPGA technology, and the implementation details of
the proposed RSA calculation architecture. Performance of several
alternative hardware architectures is discussed and compared. Finally,
conclusion is drawn, highlighting the advantages of a fully flexible
& parameterized design.
Abstract: Properly sized capacitor banks are connected across induction motors for several reasons including power factor correction, reducing distortions, increasing capacity, etc. Total harmonic distortion (THD) and power factor (PF) are used in such cases to quantify the improvements obtained through connection of the external capacitor banks. On the other hand, one of the methods for assessing the motor internal condition is by the use of Park-s pattern analysis. In spite of taking adequate precautionary measures, the capacitor banks may sometimes malfunction. Such a minor fault in the capacitor bank is often not apparently discernible. This may however, give rise to substantial degradation of power factor correction performance and may also damage the supply profile. The case is more severe with the fact that the Park-s pattern gets distorted due to such external capacitor faults, and can give anomalous results about motor internal fault analyses. The aim of this paper is to present simulation and hardware laboratory test results to have an understanding of the anomalies in harmonic distortion and Park-s pattern analyses in induction motors due to capacitor bank defects.
Abstract: In the current study we present a system that is
capable to deliver proxy based differentiated service. It will help the
carrier service node to sell a prepaid service to clients and limit the
use to a particular mobile device or devices for a certain time. The
system includes software and hardware architecture for a mobile
device with moderate computational power, and a secure protocol for
communication between it and its carrier service node. On the
carrier service node a proxy runs on a centralized server to be
capable of implementing cryptographic algorithms, while the mobile
device contains a simple embedded processor capable of executing
simple algorithms. One prerequisite is needed for the system to run
efficiently that is a presence of Global Trusted Verification Authority
(GTVA) which is equivalent to certifying authority in IP networks.
This system appears to be of great interest for many commercial
transactions, business to business electronic and mobile commerce,
and military applications.
Abstract: We developed a GPS-based navigation device for the
blind, with audio guidance in Thai language. The device is composed
of simple and inexpensive hardware components. Its user interface is
quite simple. It determines optimal routes to various landmarks in our
university campus by using heuristic search for the next waypoints.
We tested the device and made note of its limitations and possible
extensions.
Abstract: Induction motors are being used in greater numbers
throughout a wide variety of industrial and commercial applications
because it provides many benefits and reliable device to convert the
electrical energy into mechanical motion. In some application it-s
desired to control the speed of the induction motor. Because of the
physics of the induction motor the preferred method of controlling its
speed is to vary the frequency of the AC voltage driving the motor. In
recent years, with the microcontroller incorporated into an appliance
it becomes possible to use it to generate the variable frequency AC
voltage to control the speed of the induction motor.
This study investigates the microcontroller based variable
frequency power inverter. the microcontroller is provide the variable
frequency pulse width modulation (PWM) signal that control the
applied voltage on the gate drive, which is provides the required
PWM frequency with less harmonics at the output of the power
inverter.
The fully controlled bridge voltage source inverter has been
implemented with semiconductors power devices isolated gate
bipolar transistor (IGBT), and the PWM technique has been
employed in this inverter to supply the motor with AC voltage.
The proposed drive system for three & single phase power inverter
is simulated using Matlab/Simulink. The Matlab Simulation Results
for the proposed system were achieved with different SPWM. From
the result a stable variable frequency inverter over wide range has
been obtained and a good agreement has been found between the
simulation and hardware of a microcontroller based single phase
inverter.
Abstract: This paper presents an optimization of the hull
separation, i.e. transverse clearance. The main objective is to identify
the feasible speed ranges and find the optimum transverse clearance
considering the minimum wave-making resistance. The dimensions
and the weight of hardware systems installed in the catamaran
structured fuel cell powered USV (Unmanned Surface Vehicle) were
considered as constraints. As the CAE (Computer Aided Engineering)
platform FRIENDSHIP-Framework was used. The hull surface
modeling, DoE (Design of Experiment), Tangent search optimization,
tool integration and the process automation were performed by
FRIENDSHIP-Framework. The hydrodynamic result was evaluated
by XPAN the potential solver of SHIPFLOW.
Abstract: It is known that symmetric encryption algorithms are
fast and easy to implement in hardware. Also elliptic curves have
proved to be a good choice for building encryption system. Although
most of the symmetric systems have been broken, we can create a
hybrid system that has the same properties of the symmetric
encryption systems and in the same time, it has the strength of
elliptic curves in encryption. As DES algorithm is considered the
core of all successive symmetric encryption systems, we modified
DES using elliptic curves and built a new DES algorithm that is hard
to be broken and will be the core for all other symmetric systems.
Abstract: Electromyography (EMG) is the study of muscles function through analysis of electrical activity produced from muscles. This electrical activity which is displayed in the form of signal is the result of neuromuscular activation associated with muscle contraction. The most common techniques of EMG signal recording are by using surface and needle/wire electrode where the latter is usually used for interest in deep muscle. This paper will focus on surface electromyogram (SEMG) signal. During SEMG recording, several problems had to been countered such as noise, motion artifact and signal instability. Thus, various signal processing techniques had been implemented to produce a reliable signal for analysis. SEMG signal finds broad application particularly in biomedical field. It had been analyzed and studied for various interests such as neuromuscular disease, enhancement of muscular function and human-computer interface.
Abstract: In Image processing the Image compression can improve
the performance of the digital systems by reducing the cost and
time in image storage and transmission without significant reduction
of the Image quality. This paper describes hardware architecture of
low complexity Discrete Cosine Transform (DCT) architecture for
image compression[6]. In this DCT architecture, common computations
are identified and shared to remove redundant computations
in DCT matrix operation. Vector processing is a method used for
implementation of DCT. This reduction in computational complexity
of 2D DCT reduces power consumption. The 2D DCT is performed
on 8x8 matrix using two 1-Dimensional Discrete cosine transform
blocks and a transposition memory [7]. Inverse discrete cosine
transform (IDCT) is performed to obtain the image matrix and
reconstruct the original image. The proposed image compression
algorithm is comprehended using MATLAB code. The VLSI design
of the architecture is implemented Using Verilog HDL. The proposed
hardware architecture for image compression employing DCT was
synthesized using RTL complier and it was mapped using 180nm
standard cells. . The Simulation is done using Modelsim. The
simulation results from MATLAB and Verilog HDL are compared.
Detailed analysis for power and area was done using RTL compiler
from CADENCE. Power consumption of DCT core is reduced to
1.027mW with minimum area[1].
Abstract: Since communications between tag and reader in RFID
system are by radio, anyone can access the tag and obtain its any
information. And a tag always replies with the same ID so that it is
hard to distinguish between a real and a fake tag. Thus, there are many
security problems in today-s RFID System. Firstly, unauthorized
reader can easily read the ID information of any Tag. Secondly,
Adversary can easily cheat the legitimate reader using the collected
Tag ID information, such as the any legitimate Tag. These security
problems can be typically solved by encryption of messages
transmitted between Tag and Reader and by authentication for Tag.
In this paper, to solve these security problems on RFID system, we
propose the Tag Authentication Scheme based on self shrinking
generator (SSG). SSG Algorithm using in our scheme is proposed by
W.Meier and O.Staffelbach in EUROCRYPT-94. This Algorithm is
organized that only one LFSR and selection logic in order to generate
random stream. Thus it is optimized to implement the hardware logic
on devices with extremely limited resource, and the output generating
from SSG at each time do role as random stream so that it is allow our
to design the light-weight authentication scheme with security against
some network attacks. Therefore, we propose the novel tag
authentication scheme which use SSG to encrypt the Tag-ID
transmitted from tag to reader and achieve authentication of tag.
Abstract: The whole work is based on possibility to use Lego Mindstorms robotics systems to reduce costs. Lego Mindstorms consists of a wide variety of hardware components necessary to simulate, programme and test of robotics systems in practice. To programme algorithm, which simulates space using the ultrasonic sensor, was used development environment supplied with kit. Software Matlab was used to render values afterwards they were measured by ultrasonic sensor. The algorithm created for this paper uses theoretical knowledge from area of signal processing. Data being processed by algorithm are collected by ultrasonic sensor that scans 2D space in front of it. Ultrasonic sensor is placed on moving arm of robot which provides horizontal moving of sensor. Vertical movement of sensor is provided by wheel drive. The robot follows map in order to get correct positioning of measured data. Based on discovered facts it is possible to consider Lego Mindstorm for low-cost and capable kit for real-time modelling.
Abstract: Evolvable hardware (EHW) refers to a selfreconfiguration
hardware design, where the configuration is under
the control of an evolutionary algorithm (EA). A lot of research has
been done in this area several different EA have been introduced.
Every time a specific EA is chosen for solving a particular problem,
all its components, such as population size, initialization, selection
mechanism, mutation rate, and genetic operators, should be selected
in order to achieve the best results. In the last three decade a lot of
research has been carried out in order to identify the best parameters
for the EA-s components for different “test-problems". However
different researchers propose different solutions. In this paper the
behaviour of mutation rate on (1+λ) evolution strategy (ES) for
designing logic circuits, which has not been done before, has been
deeply analyzed. The mutation rate for an EHW system modifies
values of the logic cell inputs, the cell type (for example from AND
to NOR) and the circuit output. The behaviour of the mutation has
been analyzed based on the number of generations, genotype
redundancy and number of logic gates used for the evolved circuits.
The experimental results found provide the behaviour of the mutation
rate to be used during evolution for the design and optimization of
logic circuits. The researches on the best mutation rate during the last
40 years are also summarized.
Abstract: The following paper shows an interactive tool which
main purpose is to teach how to play a flute. It consists of three
stages the first one is the instruction and teaching process through a
software application, the second is the practice part when the user
starts to play the flute (hardware specially designed for this
application) this flute is capable of capturing how is being played the
flute and the final stage is the one in which the data captured are sent
to the software and the user is evaluated in order to give him / she a
correction or an acceptance
Abstract: This paper presents a VLSI design approach of a highspeed
and real-time 2-D Discrete Wavelet Transform computing. The
proposed architecture, based on new and fast convolution approach,
reduces the hardware complexity in addition to reduce the critical
path to the multiplier delay. Furthermore, an advanced twodimensional
(2-D) discrete wavelet transform (DWT)
implementation, with an efficient memory area, is designed to
produce one output in every clock cycle. As a result, a very highspeed
is attained. The system is verified, using JPEG2000
coefficients filters, on Xilinx Virtex-II Field Programmable Gate
Array (FPGA) device without accessing any external memory. The
resulting computing rate is up to 270 M samples/s and the (9,7) 2-D
wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out
memory) with 256×256 image size. In this way, the developed design
requests reduced memory and provide very high-speed processing as
well as high PSNR quality.
Abstract: According to the density of the chips, designers are
trying to put so any facilities of computational and storage on single
chips. Along with the complexity of computational and storage
circuits, the designing, testing and debugging become more and more
complex and expensive. So, hardware design will be built by using
very high speed hardware description language, which is more
efficient and cost effective. This paper will focus on the
implementation of 32-bit ALU design based on Verilog hardware
description language. Adder and subtracter operate correctly on both
unsigned and positive numbers. In ALU, addition takes most of the
time if it uses the ripple-carry adder. The general strategy for
designing fast adders is to reduce the time required to form carry
signals. Adders that use this principle are called carry look- ahead
adder. The carry look-ahead adder is to be designed with combination
of 4-bit adders. The syntax of Verilog HDL is similar to the C
programming language. This paper proposes a unified approach to
ALU design in which both simulation and formal verification can
co-exist.
Abstract: Block replacement algorithms to increase hit ratio
have been extensively used in cache memory management. Among
basic replacement schemes, LRU and FIFO have been shown to be
effective replacement algorithms in terms of hit rates. In this paper,
we introduce a flexible stack-based circuit which can be employed in
hardware implementation of both LRU and FIFO policies. We
propose a simple and efficient architecture such that stack-based
replacement algorithms can be implemented without the drawbacks
of the traditional architectures. The stack is modular and hence, a set
of stack rows can be cascaded depending on the number of blocks in
each cache set. Our circuit can be implemented in conjunction with
the cache controller and static/dynamic memories to form a cache
system. Experimental results exhibit that our proposed circuit
provides an average value of 26% improvement in storage bits and its
maximum operating frequency is increased by a factor of two