Abstract: The research will focus on creating pattern designs that are inspired by the pagodas, Phra Maha Chedi of King Rama I-IV, that are located in the temple, Wat Phra Chetuphon Vimolmangklararm Rajwaramahaviharn. Different aspects of the temple were studied, including the history, architecture, significance of the temple, and techniques used to decorate the pagodas, Phra Maha Chedi of King Rama I-IV. Moreover, composition of arts and the form of pattern designs which all led to the outcome of four Thai application pattern.
The four patterns combine Thai traditional design with international scheme, however, maintaining the distinctiveness of the glaze mosaic tiles of each Phra Maha Chedi. The patterns consist of rounded and notched petal flowers, leaves and vine, and various square shapes, and original colors which are updated for modernity. These elements are then grouped and combined with new techniques, resulting in pattern designs with modern aspects and simultaneously reflecting the charm and the aesthetic of Thai craftsmanship which are eternally embedded in the designs.
Abstract: An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
Abstract: This paper presents the 20-GHz fractional PLL (Phase
Locked Loop) circuit for the next generation Wi-Fi by using 90 nm
TSMC process. The newly suggested millimeter wave 16/17
pre-scalar is designed and verified by measurement to make the
fractional PLL having a low quantization noise. The operational
bandwidth of the 60 GHz system is 15 % of the carrier frequency
which requires large value of Kv (VCO control gain) resulting in
degradation of phase noise. To solve this problem, this paper adopts
AFC (Automatic Frequency Controller) controlled 4-bit millimeter
wave VCO with small value of Kv. Also constant Kv is implemented
using 4-bit varactor bank. The measured operational bandwidth is 18.2
~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of
-58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured
respectively. The total power consumption of the PLL is only 30 mW.
Abstract: In this report, an OTA which is used in fully
differential pipelined ADC was described. Using gain-boost
architecture with difference-ended amplifier, this OTA achieve
high-gain and high-speed. Besides, the CMFB circuit is also used, and
some methods are concerned to improve the performance. Then, by
optimization the layout design, OTA-s mismatch was reduced. This
design was using TSMC 0.18um CMOS process and simulation both
schematic and layout in Cadence. The result of the simulation shows
that the OTA has a gain up to 80dB,a unity gain bandwidth of about
1.437GHz for a 2pF load, a slew rate is about 428V/μs, a output swing
is 0.2V~1.35V, with the power supply of 1.8V, the power
consumption is 88mW. This amplifier was used in a 10bit 150MHz
pipelined ADC.
Abstract: Structural representation and technology mapping of
a Boolean function is an important problem in the design of nonregenerative
digital logic circuits (also called combinational logic
circuits). Library aware function manipulation offers a solution to
this problem. Compact multi-level representation of binary networks,
based on simple circuit structures, such as AND-Inverter Graphs
(AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR
Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter
Graphs, Reduced Boolean Circuits [8] does exist in
literature. In this work, we discuss a novel and efficient graph
realization for combinational logic circuits, represented using a
NAND-NOR-Inverter Graph (NNIG), which is composed of only
two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells.
The networks are constructed on the basis of irredundant disjunctive
and conjunctive normal forms, after factoring, comprising terms with
minimum support. Construction of a NNIG for a non-regenerative
function in normal form would be straightforward, whereas for the
complementary phase, it would be developed by considering a virtual
instance of the function. However, the choice of best NNIG for a
given function would be based upon literal count, cell count and
DAG node count of the implementation at the technology
independent stage. In case of a tie, the final decision would be made
after extracting the physical design parameters.
We have considered AIG representation for reduced disjunctive
normal form and the best of OIG/AOG/AOIG for the minimized
conjunctive normal forms. This is necessitated due to the nature of
certain functions, such as Achilles- heel functions. NNIGs are found
to exhibit 3.97% lesser node count compared to AIGs and
OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells
than AIGs and OIG/AOG/AOIGs for the various samples considered.
We compare the power efficiency and delay improvement achieved
by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for
various case studies. In comparison with functionally equivalent,
irredundant and compact AIGs, NNIGs report mean savings in power
and delay of 43.71% and 25.85% respectively, after technology
mapping with a 0.35 micron TSMC CMOS process. For a
comparison with OIG/AOG/AOIGs, NNIGs demonstrate average
savings in power and delay by 47.51% and 24.83%. With respect to
device count needed for implementation with static CMOS logic
style, NNIGs utilize 37.85% and 33.95% lesser transistors than their
AIG and OIG/AOG/AOIG counterparts.
Abstract: This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.
Abstract: New methodologies for XOR-XNOR circuits are
proposed to improve the speed and power as these circuits are basic
building blocks of many arithmetic circuits. This paper evaluates and
compares the performance of various XOR-XNOR circuits. The
performance of the XOR-XNOR circuits based on TSMC 0.18μm
process models at all range of the supply voltage starting from 0.6V
to 3.3V is evaluated by the comparison of the simulation results
obtained from HSPICE. Simulation results reveal that the proposed
circuit exhibit lower PDP and EDP, more power efficient and faster
when compared with best available XOR-XNOR circuits in the
literature.
Abstract: In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.
Abstract: Despite so many years- development, the mainstream of workflow solutions from IT industries has not made ad-hoc workflow-support easy or inexpensive in MIS. Moreover, most of academic approaches tend to make their resulted BPM (Business Process Management) more complex and clumsy since they used to necessitate modeling workflow. To cope well with various ad-hoc or casual requirements on workflows while still keeping things simple and inexpensive, the author puts forth first the TSM design pattern that can provide a flexible workflow control while minimizing demand of predefinitions and modeling workflow, which introduces a generic approach for building BPM in workflow-aware MISs (Management Information Systems) with low development and running expenses.
Abstract: A active inductor in CMOS techonology with a supply voltage of 1.8V is presented. The value of the inductance L can be in the range from 0.12nH to 0.25nH in high frequency(HF). The proposed active inductor is designed in TSMC 0.18-um CMOS technology. The power dissipation of this inductor can retain constant at all operating frequency bands and consume around 20mW from 1.8V power supply. Inductors designed by integrated circuit occupy much smaller area, for this reason,attracted researchers attention for more than decade. In this design we used Advanced Designed System (ADS) for simulating cicuit.
Abstract: Today-s economy is in a permanent change, causing
merger and acquisitions and co operations between enterprises. As a
consequence, process adaptations and realignments result in systems
integration and software development projects. Processes and
procedures to execute such projects are still reliant on craftsman-ship
of highly skilled workers. A generally accepted, industrialized
production, characterized by high efficiency and quality, seems
inevitable.
In spite of this, current concepts of software industrialization are
aimed at traditional software engineering and do not consider the
characteristics of systems integration. The present work points out
these particularities and discusses the applicability of existing
industrial concepts in the systems integration domain. Consequently
it defines further areas of research necessary to bring the field of
systems integration closer to an industrialized production, allowing a
higher efficiency, quality and return on investment.
Abstract: Parallel Prefix addition is a technique for improving
the speed of binary addition. Due to continuing integrating intensity
and the growing needs of portable devices, low-power and highperformance
designs are of prime importance. The classical parallel
prefix adder structures presented in the literature over the years
optimize for logic depth, area, fan-out and interconnect count of logic
circuits. In this paper, a new architecture for performing 8-bit, 16-bit
and 32-bit Parallel Prefix addition is proposed. The proposed prefix
adder structures is compared with several classical adders of same
bit width in terms of power, delay and number of computational
nodes. The results reveal that the proposed structures have the least
power delay product when compared with its peer existing Prefix
adder structures. Tanner EDA tool was used for simulating the adder
designs in the TSMC 180 nm and TSMC 130 nm technologies.
Abstract: A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology.With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.
Abstract: A spanning tree of a connected graph is a tree which
consists the set of vertices and some or perhaps all of the edges from
the connected graph. In this paper, a model for spanning tree
transformation of connected graphs into single-row networks, namely
Spanning Tree of Connected Graph Modeling (STCGM) will be
introduced. Path-Growing Tree-Forming algorithm applied with
Vertex-Prioritized is contained in the model to produce the spanning
tree from the connected graph. Paths are produced by Path-Growing
and they are combined into a spanning tree by Tree-Forming. The
spanning tree that is produced from the connected graph is then
transformed into single-row network using Tree Sequence Modeling
(TSM). Finally, the single-row routing problem is solved using a
method called Enhanced Simulated Annealing for Single-Row
Routing (ESSR).
Abstract: This paper discusses a new, systematic approach to
the synthesis of a NP-hard class of non-regenerative Boolean
networks, described by FON[FOFF]={mi}[{Mi}], where for every
mj[Mj]∈{mi}[{Mi}], there exists another mk[Mk]∈{mi}[{Mi}], such
that their Hamming distance HD(mj, mk)=HD(Mj, Mk)=O(n), (where
'n' represents the number of distinct primary inputs). The method
automatically ensures exact minimization for certain important selfdual
functions with 2n-1 points in its one-set. The elements meant for
grouping are determined from a newly proposed weighted incidence
matrix. Then the binary value corresponding to the candidate pair is
correlated with the proposed binary value matrix to enable direct
synthesis. We recommend algebraic factorization operations as a post
processing step to enable reduction in literal count. The algorithm
can be implemented in any high level language and achieves best
cost optimization for the problem dealt with, irrespective of the
number of inputs. For other cases, the method is iterated to
subsequently reduce it to a problem of O(n-1), O(n-2),.... and then
solved. In addition, it leads to optimal results for problems exhibiting
higher degree of adjacency, with a different interpretation of the
heuristic, and the results are comparable with other methods.
In terms of literal cost, at the technology independent stage, the
circuits synthesized using our algorithm enabled net savings over
AOI (AND-OR-Invert) logic, AND-EXOR logic (EXOR Sum-of-
Products or ESOP forms) and AND-OR-EXOR logic by 45.57%,
41.78% and 41.78% respectively for the various problems.
Circuit level simulations were performed for a wide variety of
case studies at 3.3V and 2.5V supply to validate the performance of
the proposed method and the quality of the resulting synthesized
circuits at two different voltage corners. Power estimation was
carried out for a 0.35micron TSMC CMOS process technology. In
comparison with AOI logic, the proposed method enabled mean
savings in power by 42.46%. With respect to AND-EXOR logic, the
proposed method yielded power savings to the tune of 31.88%, while
in comparison with AND-OR-EXOR level networks; average power
savings of 33.23% was obtained.
Abstract: The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.
Abstract: The paper shows how the perceptions of five organizational virtuousness dimensions (optimism, trust, compassion, integrity, and forgiveness) explain organizational citizenship behaviors (altruism, sportsmanship, courtesy, conscientiousness, and civic virtue). A sample comprising 216 individuals from 14 industrial organizations was collected. Individuals reported their perceptions of organizational virtuousness, their organizational citizenship behaviors (OCB) being reported by their supervisors. The main findings are the following: (a) the perceptions of trust predict altruism; (b) the perceptions of integrity predict civic virtue.
Abstract: A way of generating millimeter wave I/Q signal using inductive resonator matched poly-phase filter is suggested. Normally the poly-phase filter generates quite accurate I/Q phase and magnitude but the loss of the filter is considerable due to series connection of passive RC components. This loss term directly increases system noise figure when the poly-phase filter is used in RF Front-end. The proposed matching method eliminates above mentioned loss and in addition provides gain on the passive filter. The working algorithm is illustrated by mathematical analysis. The generated I/Q signal is used in implementing millimeter wave phase shifter for the 60 GHz communication system to verify its effectiveness. The circuit is fabricated in 90 nm TSMC RF CMOS process under 1.2 V supply voltage. The measurement results showed that the suggested method improved gain by 6.5 dB and noise by 2.3 dB. The summary of the proposed I/Q generation is compared with previous works.
Abstract: This paper introduces an adiabatic register file based
on two-phase CPAL (Complementary Pass-Transistor Adiabatic
Logic circuits) with power-gating scheme, which can operate on a
single-phase power clock. A 32×32 single-phase adiabatic register file
with power-gating scheme has been implemented with TSMC 0.18μm
CMOS technology. All the circuits except for the storage cells employ
two-phase CPAL circuits, and the storage cell is based on the
conventional memory one. The two-phase non-overlap power-clock
generator with power-gating scheme is used to supply the proposed
adiabatic register file. Full-custom layouts are drawn. The energy and
functional simulations have been performed using the net-list
extracted from their layouts. Compared with the traditional static
CMOS register file, HSPICE simulations show that the proposed
adiabatic register file can work very well, and it attains about 73%
energy savings at 100 MHz.