20 GHz Fractional Phased Locked Loop Circuit for the Gbps Wireless Communication

This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.

Authors:

• Ki-Jin Kim
• Sanghoon Park
• K. H. Ahn

Keywords:

• Millimeter Wave Fractional PLL
• Wide band VCO
• WPAN Transceiver.

References:

[1] K. Okada, N. Li, K. Matsushita, K. Bunsen, R. Murakami, A. Musa, T.
Sato, H. Asada, N. Takayama, S. Ito, W. Chaivipas, R. Minami, T.
Yamaguchi, Y. Takeuchi, H. Yamagishi, M. Noda, and A. Matsuzawa, "A
60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for
IEEE 802.15.3c," IEEE Journal of Solid State Circuits, vol. 46, no. 12,
pp 2988-3004, Dec 2011.
[2] F. Barale, P Sen, S. Sarkar, S. Pinel, and J. Laskar, "A 60GHz-Standard
Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm
CMOS," IEEE Microwave and Wireless Components Letters., vol. 20, no.
7, pp.411-413, July 2010.
[3] Ja-Yol Lee, S. H. Lee, H. Kim, and H. K. Yu, "A 28.5-32.5-GHz Fast
Settling Multichannel PLL Synthesizer for 60-GHz WPAN Radio,"
IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp.1234-1246, May
2008.
[4] B. Catli and M. Hella, "A 60 GHz CMOS Combined mm-wave
VCO/Divider with 10-GHz Tuning Range," CICC, 2009, pp 665-668.
[5] C. Lee, L. C. Cho, J. H. Wu, and S. I. Liu, "A 50.8-53 GHz Clock
Generator Using a Harmonic-Locked PD in 0.13 CMOS," TCASII, vol. 55,
no. 5, pp. 404-408, May 2008.
[6] H. Knapp, T. F. Meister, M. Wurzer, K. Aufinger, S. Boguth, and L.
Treitinger, "A Low Power 20 GHz SiGe Dual-Modulus Prescaler,"
IEEE MTT-S Digest, pp 731-734, 2000.
[7] M. A. Do, X. P. Yu, J. G. Ma, K. S. Yeo, R. Wu, and Q. Z. Zhang, "A
2GHz Programmable Counter with new re-loadable D Flip-flop," IEEE
EDSSC, pp 269-272, 2003.