Abstract: Acute toxicity of nano SiO2, ZnO, MCM-41 (Meso
pore silica), Cu, Multi Wall Carbon Nano Tube (MWCNT), Single
Wall Carbon Nano Tube (SWCNT) , Fe (Coated) to bacteria Vibrio
fischeri using a homemade luminometer , was evaluated. The values
of the nominal effective concentrations (EC), causing 20% and 50%
inhibition of biouminescence, using two mathematical models at two
times of 5 and 30 minutes were calculated. Luminometer was
designed with Photomultiplier (PMT) detector. Luminol
chemiluminescence reaction was carried out for the calibration graph.
In the linear calibration range, the correlation coefficients and
coefficient of Variation (CV) were 0.988 and 3.21% respectively
which demonstrate the accuracy and reproducibility of the instrument
that are suitable. The important part of this research depends on how
to optimize the best condition for maximum bioluminescence. The
culture of Vibrio fischeri with optimal conditions in liquid media,
were stirring at 120 rpm at a temperature of 150C to 180C and were
incubated for 24 to 72 hours while solid medium was held at 180C
and for 48 hours. Suspension of nanoparticles ZnO, after 30 min
contact time to bacteria Vibrio fischeri, showed the highest toxicity
while SiO2 nanoparticles showed the lowest toxicity. After 5 min
exposure time, the toxicity of ZnO was the strongest and MCM-41
was the weakest toxicant component.
Abstract: This paper addresses the problem of asymptotic tracking
control of a linear parabolic partial differential equation with indomain
point actuation. As the considered model is a non-standard
partial differential equation, we firstly developed a map that allows
transforming this problem into a standard boundary control problem
to which existing infinite-dimensional system control methods can
be applied. Then, a combination of energy multiplier and differential
flatness methods is used to design an asymptotic tracking controller.
This control scheme consists of stabilizing state-feedback derived
from the energy multiplier method and feed-forward control based
on the flatness property of the system. This approach represents
a systematic procedure to design tracking control laws for a class
of partial differential equations with in-domain point actuation. The
applicability and system performance are assessed by simulation
studies.
Abstract: In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.
Abstract: The flexible follower response of a translating cam with
four different profiles for rise-dwell-fall-dwell (RDFD) motion is
investigated. The cycloidal displacement motion, the modified
sinusoidal acceleration motion, the modified trapezoidal acceleration
motion, and the 3-4-5 polynomial motion are employed to describe the
rise and the fall motions of the follower and the associated four kinds of
cam profiles are studied. Since the follower flexibility is considered,
the contact point of the roller and the cam is an unknown. Two
geometric constraints formulated to restrain the unknown position are
substituted into Hamilton-s principle with Lagrange multipliers.
Applying the assumed mode method, one can obtain the governing
equations of motion as non-linear differential-algebraic equations. The
equations are solved using Runge-Kutta method. Then, the responses of
the flexible follower undergoing the four different motions are
investigated in time domain and in frequency domain.
Abstract: This paper presents the influence of distributed generation (DG) on congestion and locational marginal price (LMP) in an optimal power flow (OPF) based wholesale electricity market. The problem of optimal placement to manage congestion and reduce LMP is formulated for the objective of social welfare maximization. From competitive electricity market standpoint, DGs have great value when they reduce load in particular locations and at particular times when feeders are heavily loaded. The paper lies on the groundwork that solution to optimal mix of generation and transmission resources can be achieved by addressing congestion and corresponding LMP. Obtained as lagrangian multiplier associated with active power flow equation for each node, LMP gives the short run marginal cost (SRMC) of electricity. Specific grid locations are examined to study the influence of DG penetration on congestion and corresponding shadow prices. The influence of DG on congestion and locational marginal prices has been demonstrated in a modified IEEE 14 bus test system.
Abstract: In this study, we are interested in the economic lot
scheduling problem (ELSP) that considers manufacturing of the
serviceable products and remanufacturing of the reworked products. In
this paper, we formulate a mathematical model for the ELSP with
reworks using the basic period approach. In order to solve this
problem, we propose a search algorithm to find the cyclic multiplier ki
of each product that can be cyclically produced for every ki basic
periods. This research also uses two heuristics to search for the optimal
production sequence of all lots and the optimal time length of the basic
period so as to minimize the average total cost. This research uses a
numerical example to show the effectiveness of our approach.
Abstract: This paper describes the pipeline architecture of
high-speed modified Booth multipliers. The proposed multiplier
circuits are based on the modified Booth algorithm and the pipeline
technique which are the most widely used to accelerate the
multiplication speed. In order to implement the optimally pipelined
multipliers, many kinds of experiments have been conducted. The
speed of the multipliers is greatly improved by properly deciding the
number of pipeline stages and the positions for the pipeline registers to
be inserted. We described the proposed modified Booth multiplier
circuits in Verilog HDL and synthesized the gate-level circuits using
0.13um standard cell library. The resultant multiplier circuits show
better performance than others. Since the proposed multipliers operate
at GHz ranges, they can be used in the systems requiring very high
performance.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: Truncated multiplier is a good candidate for digital
signal processing (DSP) applications including finite impulse
response (FIR) and discrete cosine transform (DCT). Through
truncated multiplier a significant reduction in Field Programmable
Gate Array (FPGA) resources can be achieved. This paper presents
for the first time a comparison of resource utilization of Spartan-3AN
and Virtex-5 implementation of standard and truncated multipliers
using Very High Speed Integrated Circuit Hardware Description
Language (VHDL). The Virtex-5 FPGA shows significant
improvement as compared to Spartan-3AN FPGA device. The
Virtex-5 FPGA device shows better performance with a percentage
ratio of number of occupied slices for standard to truncated
multipliers is increased from 40% to 73.86% as compared to Spartan-
3AN is decreased from 68.75% to 58.78%. Results show that the
anomaly in Spartan-3AN FPGA device average connection and
maximum pin delay have been efficiently reduced in Virtex-5 FPGA
device.
Abstract: Calibration estimation is a method of adjusting the
original design weights to improve the survey estimates by using
auxiliary information such as the known population total (or mean)
of the auxiliary variables. A calibration estimator uses calibrated
weights that are determined to minimize a given distance measure to
the original design weights while satisfying a set of constraints
related to the auxiliary information. In this paper, we propose a new
multivariate calibration estimator for the population mean in the
stratified sampling design, which incorporates information available
for more than one auxiliary variable. The problem of determining the
optimum calibrated weights is formulated as a Mathematical
Programming Problem (MPP) that is solved using the Lagrange
multiplier technique.
Abstract: In this paper a new fast simplification method is presented. Such method realizes Karnough map with large number of variables. In order to accelerate the operation of the proposed method, a new approach for fast detection of group of ones is presented. Such approach implemented in the frequency domain. The search operation relies on performing cross correlation in the frequency domain rather than time one. It is proved mathematically and practically that the number of computation steps required for the presented method is less than that needed by conventional cross correlation. Simulation results using MATLAB confirm the theoretical computations. Furthermore, a powerful solution for realization of complex functions is given. The simplified functions are implemented by using a new desigen for neural networks. Neural networks are used because they are fault tolerance and as a result they can recognize signals even with noise or distortion. This is very useful for logic functions used in data and computer communications. Moreover, the implemented functions are realized with minimum amount of components. This is done by using modular neural nets (MNNs) that divide the input space into several homogenous regions. Such approach is applied to implement XOR function, 16 logic functions on one bit level, and 2-bit digital multiplier. Compared to previous non- modular designs, a clear reduction in the order of computations and hardware requirements is achieved.
Abstract: In this paper, a novel approach is presented
for designing multiplier-free state-space digital filters. The
multiplier-free design is obtained by finding power-of-2 coefficients
and also quantizing the state variables to power-of-2
numbers. Expressions for the noise variance are derived for the
quantized state vector and the output of the filter. A “structuretransformation
matrix" is incorporated in these expressions. It
is shown that quantization effects can be minimized by properly
designing the structure-transformation matrix. Simulation
results are very promising and illustrate the design algorithm.
Abstract: The globe Sustainability has become the subject of international attention, the key reason is that global climate change. Climate and disasters around the abnormal frequency multiplier, the global temperature of the catastrophe and disaster continue to occur throughout the world, as well as countries around the world. Currently there are many important international conferences and policy, it is a "global environmental sustainability " and "living human health " as the goal of development, including the APEC 2007 meeting to "climate Clean Energy" as the theme Sydney Declaration, 2008 World Economic Forum's "Carbon - promote Cool Earth energy efficiency improvement project", the EU proposed "Green Idea" program, the Japanese annual policy, "low-carbon society, sustainable eco-city environment (Eco City) "And from 2009 to 2010 to promote the "Eco-Point" to promote green energy and carbon reduction products .And the 2010 World Climate Change Conference (COP16 United Nations Climate Change Conference Copenhagen), the world has been the subject of Negative conservative "Environmental Protection ", "save energy consumption, " into a positive response to the "Sustainable " and" LOHAS", while Taiwan has actively put forward eco-cities, green building, green building materials and other related environmental response Measures, especially green building construction environment that is the basis of factors, the most widely used application level, and direct contact with human health and the key to sustainable planet. "Sustainable development "is a necessary condition for continuation of the Earth, "healthy and comfortable" is a necessary condition for the continuation of life, and improve the "quality" is a necessary condition for economic development, balance between the three is "to enhance the efficiency of ", According to the World Business Council for Sustainable Development (WBCSD) for the "environmental efficiency "(Eco-Efficiency) proposed: " the achievement of environmental efficiency, the price to be competitive in the provision of goods or services to meet people's needs, improve living Quality at the same time, the goods or services throughout the life cycle. Its impact on the environment and natural resource utilization and gradually reduced to the extent the Earth can load. "whichever is the economy "Economic" and " Ecologic". The research into the methodology to obtain the Taiwan Green Building Material Labeling product as the scope of the study, by investigating and weight analysis to explore green building environmental load (Ln) factor and the Green Building Quality (Qn) factor to Establish green building environmental efficiency assessment model (GBM Eco-Efficiency). And building materials for healthy green label products for priority assessment object, the object is set in the material evidence for the direct response to the environmental load from the floor class-based, explicit feedback correction to the Green Building environmental efficiency assessment model, "efficiency " as a starting point to achieve balance between human "health "and Earth "sustainable development of win-win strategy. The study is expected to reach 1.To establish green building materials and the quality of environmental impact assessment system, 2. To establish value of GBM Eco-Efficiency model, 3. To establish the GBM Eco-Efficiency model for application of green building material feedback mechanisms.
Abstract: Long number multiplications (n ≥ 128-bit) are a
primitive in most cryptosystems. They can be performed better by
using Karatsuba-Ofman technique. This algorithm is easy to
parallelize on workstation network and on distributed memory, and
it-s known as the practical method of choice. Multiplying long
numbers using Karatsuba-Ofman algorithm is fast but is highly
recursive. In this paper, we propose different designs of
implementing Karatsuba-Ofman multiplier. A mixture of sequential
and combinational system design techniques involving pipelining is
applied to our proposed designs. Multiplying large numbers can be
adapted flexibly to time, area and power criteria. Computationally
and occupation constrained in embedded systems such as: smart
cards, mobile phones..., multiplication of finite field elements can be
achieved more efficiently. The proposed designs are compared to
other existing techniques. Mathematical models (Area (n), Delay (n))
of our proposed designs are also elaborated and evaluated on
different FPGAs devices.
Abstract: In the present paper, we investigate a differential subordination
involving multiplier transformation related to a sector in the
open unit disk E = {z : |z| < 1}. As special cases to our main
result, certain sufficient conditions for strongly starlike and strongly
convex functions are obtained.
Abstract: For higher order multiplications, a huge number of
adders or compressors are to be used to perform the partial product
addition. We have reduced the number of adders by introducing
special kind of adders that are capable to add five/six/seven bits per
decade. These adders are called compressors. Binary counter
property has been merged with the compressor property to develop
high order compressors. Uses of these compressors permit the
reduction of the vertical critical paths. A 16×16 bit multiplier has
been developed using these compressors. These compressors make
the multipliers faster as compared to the conventional design that
have been used 4-2 compressors and 3-2 compressors.
Abstract: In this paper, the hardware implementation of the
RSA public-key cryptographic algorithm is presented. The RSA
cryptographic algorithm is depends on the computation of repeated
modular exponentials.
The Montgomery algorithm is used and modified to reduce
hardware resources and to achieve reasonable operating speed for
FPGA. An efficient architecture for modular multiplications based on
the array multiplier is proposed. We have implemented a RSA
cryptosystem based on Montgomery algorithm. As a result, it is
shown that proposed architecture contributes to small area and
reasonable speed.
Abstract: An original Direct Numerical Simulation (DNS) method to tackle the problem of particulate flows at moderate to high concentration and finite Reynolds number is presented. Our method is built on the framework established by Glowinski and his coworkers [1] in the sense that we use their Distributed Lagrange Multiplier/Fictitious Domain (DLM/FD) formulation and their operator-splitting idea but differs in the treatment of particle collisions. The novelty of our contribution relies on replacing the simple artificial repulsive force based collision model usually employed in the literature by an efficient Discrete Element Method (DEM) granular solver. The use of our DEM solver enables us to consider particles of arbitrary shape (at least convex) and to account for actual contacts, in the sense that particles actually touch each other, in contrast with the simple repulsive force based collision model. We recently upgraded our serial code, GRIFF 1 [2], to full MPI capabilities. Our new code, PeliGRIFF 2, is developed under the framework of the full MPI open source platform PELICANS [3]. The new MPI capabilities of PeliGRIFF open new perspectives in the study of particulate flows and significantly increase the number of particles that can be considered in a full DNS approach: O(100000) in 2D and O(10000) in 3D. Results on the 2D/3D sedimentation/fluidization of isometric polygonal/polyedral particles with collisions are presented.
Abstract: This paper presents a VLSI design approach of a highspeed
and real-time 2-D Discrete Wavelet Transform computing. The
proposed architecture, based on new and fast convolution approach,
reduces the hardware complexity in addition to reduce the critical
path to the multiplier delay. Furthermore, an advanced twodimensional
(2-D) discrete wavelet transform (DWT)
implementation, with an efficient memory area, is designed to
produce one output in every clock cycle. As a result, a very highspeed
is attained. The system is verified, using JPEG2000
coefficients filters, on Xilinx Virtex-II Field Programmable Gate
Array (FPGA) device without accessing any external memory. The
resulting computing rate is up to 270 M samples/s and the (9,7) 2-D
wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out
memory) with 256×256 image size. In this way, the developed design
requests reduced memory and provide very high-speed processing as
well as high PSNR quality.
Abstract: For gamma radiation detection, assemblies having
scintillation crystals and a photomultiplier tube, also there is a
preamplifier connected to the detector because the signals from
photomultiplier tube are of small amplitude. After pre-amplification
the signals are sent to the amplifier and then to the multichannel
analyser. The multichannel analyser sorts all incoming electrical
signals according to their amplitudes and sorts the detected photons
in channels covering small energy intervals. The energy range of
each channel depends on the gain settings of the multichannel
analyser and the high voltage across the photomultiplier tube. The
exit spectrum data of the two main isotopes studied ,putting data in
biomass program ,process it by Matlab program to get the solid
holdup image (solid spherical nuclear fuel)