Abstract: The growth and interconnection of power networks in many regions has invited complicated techniques for energy management services (EMS). State estimation techniques become a powerful tool in power system control centers, and that more information is required to achieve the objective of EMS. For the online state estimator, assuming the continuous time is equidistantly sampled with period Δt, processing events must be finished within this period. Advantage of Kalman Filtering (KF) algorithm in using system information to improve the estimation precision is utilized. Computational power is a major issue responsible for the achievement of the objective, i.e. estimators- solution at a small sampled period. This paper presents the optimum utilization of processors in a state estimator based on KF. The model used is presented using Petri net (PN) theory.
Abstract: Concurrency and synchronization are becoming big
issues as every new PC comes with multi-core processors. A major
reason for Object-Oriented Programming originally was to enable
easier reuse: encode your algorithm into a class and thoroughly
debug it, then you can reuse the class again and again. However,
when we get to concurrency and synchronization, this is often not
possible. Thread-safety issues means that synchronization constructs
need to be entangled into every class involved. We contributed a
detailed literature review of issues and challenges in concurrent
programming and present a methodology that uses the Aspect-
Oriented paradigm to address this problem. Aspects will allow us to
extract the synchronization concerns as schemes to be “weaved in"
later into the main code. This allows the aspects to be separately
tested and verified. Hence, the functional components can be weaved
with reusable synchronization schemes that are robust and scalable.
Abstract: When a small H/W IP is designed, we can develop an
appropriate verification environment by observing the simulated
signal waves, or using the serial test vectors for the fixed output. In the
case of design and verification of a massive parallel processor with
multiple IPs, it-s difficult to make a verification system with existing
common verification environment, and to verify each partial IP. A
TestDrive verification environment can build easy and reliable
verification system that can produce highly intuitive results by
applying Modelsim and SystemVerilog-s DPI. It shows many
advantages, for example a high-level design of a GPGPU processor
design can be migrate to FPGA board immediately.
Abstract: A prototype of an anomaly detection system was
developed to automate process of recognizing an anomaly of
roentgen image by utilizing fuzzy histogram hyperbolization image
enhancement and back propagation artificial neural network.
The system consists of image acquisition, pre-processor, feature
extractor, response selector and output. Fuzzy Histogram
Hyperbolization is chosen to improve the quality of the roentgen
image. The fuzzy histogram hyperbolization steps consist of
fuzzyfication, modification of values of membership functions and
defuzzyfication. Image features are extracted after the the quality of
the image is improved. The extracted image features are input to the
artificial neural network for detecting anomaly. The number of nodes
in the proposed ANN layers was made small.
Experimental results indicate that the fuzzy histogram
hyperbolization method can be used to improve the quality of the
image. The system is capable to detect the anomaly in the roentgen
image.
Abstract: Conventional approaches in the implementation of logic programming applications on embedded systems are solely of software nature. As a consequence, a compiler is needed that transforms the initial declarative logic program to its equivalent procedural one, to be programmed to the microprocessor. This approach increases the complexity of the final implementation and reduces the overall system's performance. On the contrary, presenting hardware implementations which are only capable of supporting logic programs prevents their use in applications where logic programs need to be intertwined with traditional procedural ones, for a specific application. We exploit HW/SW codesign methods to present a microprocessor, capable of supporting hybrid applications using both programming approaches. We take advantage of the close relationship between attribute grammar (AG) evaluation and knowledge engineering methods to present a programmable hardware parser that performs logic derivations and combine it with an extension of a conventional RISC microprocessor that performs the unification process to report the success or failure of those derivations. The extended RISC microprocessor is still capable of executing conventional procedural programs, thus hybrid applications can be implemented. The presented implementation is programmable, supports the execution of hybrid applications, increases the performance of logic derivations (experimental analysis yields an approximate 1000% increase in performance) and reduces the complexity of the final implemented code. The proposed hardware design is supported by a proposed extended C-language called C-AG.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: A low cost Short Message System (SMS) based Home security system equipped with motion, smoke, temperature, humidity and light sensors has been studied and tested. The sensors are controlled by a microprocessor PIC 18F4520 through the SMS having password protection code for the secure operation. The user is able to switch light and the appliances and get instant feedback. Also in cases of emergencies such as fire or robbery the system will send alert message to occupant and relevant civil authorities. The operation of the home security has been tested on Vodafone- Fiji network and Digicel Fiji Network for emergency and feedback responses for 25 samples. The experiment showed that it takes about 8-10s for the security system to respond in case of emergency. It takes about 18-22s for the occupant to switch and monitor lights and appliances and then get feedback depending upon the network traffic.
Abstract: Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
Abstract: This paper presents a new hardware interface using a
microcontroller which processes audio music signals to standard
MIDI data. A technique for processing music signals by extracting
note parameters from music signals is described. An algorithm to
convert the voice samples for real-time processing without complex
calculations is proposed. A high frequency microcontroller as the
main processor is deployed to execute the outlined algorithm. The
MIDI data generated is transmitted using the EIA-232 protocol. The
analyses of data generated show the feasibility of using
microcontrollers for real-time MIDI generation hardware interface.
Abstract: Exploring an autistic child in Elementary school is a
difficult task that must be fully thought out and the teachers should
be aware of the many challenges they face raising their child
especially the behavioral problems of autistic children. Hence there
arises a need for developing Artificial intelligence (AI)
Contemporary Techniques to help diagnosis to discover autistic
people.
In this research, we suggest designing architecture of expert
system that combine Cognitive Maps (CM) with Case Based
Reasoning technique (CBR) in order to reduce time and costs of
traditional diagnosis process for the early detection to discover
autistic children. The teacher is supposed to enter child's information
for analyzing by CM module. Then, the reasoning processor would
translate the output into a case to be solved a current problem by
CBR module. We will implement a prototype for the model as a
proof of concept using java and MYSQL.
This will be provided a new hybrid approach that will achieve new
synergies and improve problem solving capabilities in AI. And we
will predict that will reduce time, costs, the number of human errors
and make expertise available to more people who want who want to
serve autistic children and their families.
Abstract: Scale Time Offset Robust Modulation (STORM) [1]–
[3] is a high bandwidth waveform design that adds time-scale
to embedded reference modulations using only time-delay [4]. In
an environment where each user has a specific delay and scale,
identification of the user with the highest signal power and that
user-s phase is facilitated by the STORM processor. Both of these
parameters are required in an efficient multiuser detection algorithm.
In this paper, the STORM modulation approach is evaluated with
a direct sequence spread quadrature phase shift keying (DS-QPSK)
system. A misconception of the STORM time scale modulation is that
a fine temporal resolution is required at the receiver. STORM will
be applied to a QPSK code division multiaccess (CDMA) system
by modifying the spreading codes. Specifically, the in-phase code
will use a typical spreading code, and the quadrature code will
use a time-delayed and time-scaled version of the in-phase code.
Subsequently, the same temporal resolution in the receiver is required
before and after the application of STORM. In this paper, the bit error
performance of STORM in a synchronous CDMA system is evaluated
and compared to theory, and the bit error performance of STORM
incorporated in a single user WCDMA downlink is presented to
demonstrate the applicability of STORM in a modern communication
system.
Abstract: Like other external sorting algorithms, the presented
algorithm is a two step algorithm including internal and external
steps. The first part of the algorithm is like the other similar
algorithms but second part of that is including a new easy
implementing method which has reduced the vast number of inputoutput
operations saliently. As decreasing processor operating time
does not have any effect on main algorithm speed, any improvement
in it should be done through decreasing the number of input-output
operations. This paper propose an easy algorithm for choose the
correct record location of the final list. This decreases the time
complexity and makes the algorithm faster.
Abstract: This paper is on the general discussion of memory consistency model like Strict Consistency, Sequential Consistency, Processor Consistency, Weak Consistency etc. Then the techniques for implementing distributed shared memory Systems and Synchronization Primitives in Software Distributed Shared Memory Systems are discussed. The analysis involves the performance measurement of the protocol concerned that is Multiple Writer Protocol. Each protocol has pros and cons. So, the problems that are associated with each protocol is discussed and other related things are explored.
Abstract: This project relates to a two-wheeled self balancing
robot for transferring loads on different locations along a path. This
robot specifically functions as a dual mode navigation to navigate
efficiently along a desired path. First, as a plurality of distance
sensors mounted at both sides of the body for collecting information
on tilt angle of the body and second, as a plurality of speed sensors
mounted at the bottom of the body for collecting information of the
velocity of the body in relative to the ground. A microcontroller for
processing information collected from the sensors and configured to
set the path and to balance the body automatically while a processor
operatively coupled to the microcontroller and configured to compute
change of the tilt and velocity of the body. A direct current motor
operatively coupled to the microcontroller for controlling the wheels
and characterized in that a remote control is operatively coupled to
the microcontroller to operate the robot in dual navigation modes.
Abstract: Traditional parallel single string matching algorithms
are always based on PRAM computation model. Those algorithms
concentrate on the cost optimal design and the theoretical speed.
Based on the distributed string matching algorithm proposed by
CHEN, a practical distributed string matching algorithm architecture
is proposed in this paper. And also an improved single string matching
algorithm based on a variant Boyer-Moore algorithm is presented. We
implement our algorithm on the above architecture and the
experiments prove that it is really practical and efficient on distributed
memory machine. Its computation complexity is O(n/p + m), where n
is the length of the text, and m is the length of the pattern, and p is the
number of the processors.
Abstract: This paper describes the design of a voltage based maximum power point tracker (MPPT) for photovoltaic (PV) applications. Of the various MPPT methods, the voltage based method is considered to be the simplest and cost effective. The major disadvantage of this method is that the PV array is disconnected from the load for the sampling of its open circuit voltage, which inevitably results in power loss. Another disadvantage, in case of rapid irradiance variation, is that if the duration between two successive samplings, called the sampling period, is too long there is a considerable loss. This is because the output voltage of the PV array follows the unchanged reference during one sampling period. Once a maximum power point (MPP) is tracked and a change in irradiation occurs between two successive samplings, then the new MPP is not tracked until the next sampling of the PV array voltage. This paper proposes an MPPT circuit in which the sampling interval of the PV array voltage, and the sampling period have been shortened. The sample and hold circuit has also been simplified. The proposed circuit does not utilize a microcontroller or a digital signal processor and is thus suitable for low cost and low power applications.
Abstract: OpenMP is an API for parallel programming model of shared memory multiprocessors. Novice OpenMP programmers often produce the code that compiler cannot find human errors. It was investigated how compiler coped with the common mistakes that can occur in OpenMP code. The latest version(4.4.3) of GCC is used for this research. It was found that GCC compiled the codes without any errors or warnings. In this paper the programming aid tool is presented for OpenMP programs. It can check 12 common mistakes that novice programmer can commit during the programming of OpenMP. It was demonstrated that the programming aid tool can detect the various common mistakes that GCC failed to detect.
Abstract: In order to make conventional implicit algorithm to be applicable in large scale parallel computers , an interface prediction and correction of discontinuous finite element method is presented to solve time-dependent neutron transport equations under 2-D cylindrical geometry. Domain decomposition is adopted in the computational domain.The numerical experiments show that our parallel algorithm with explicit prediction and implicit correction has good precision, parallelism and simplicity. Especially, it can reach perfect speedup even on hundreds of processors for large-scale problems.
Abstract: Model Predictive Control (MPC) is increasingly being
proposed for real time applications and embedded systems. However
comparing to PID controller, the implementation of the MPC in
miniaturized devices like Field Programmable Gate Arrays (FPGA)
and microcontrollers has historically been very small scale due to its
complexity in implementation and its computation time requirement.
At the same time, such embedded technologies have become an
enabler for future manufacturing enterprises as well as a transformer
of organizations and markets. Recently, advances in microelectronics
and software allow such technique to be implemented in embedded
systems. In this work, we take advantage of these recent advances
in this area in the deployment of one of the most studied and
applied control technique in the industrial engineering. In fact in
this paper, we propose an efficient framework for implementation
of Generalized Predictive Control (GPC) in the performed STM32
microcontroller. The STM32 keil starter kit based on a JTAG interface
and the STM32 board was used to implement the proposed GPC
firmware. Besides the GPC, the PID anti windup algorithm was
also implemented using Keil development tools designed for ARM
processor-based microcontroller devices and working with C/Cµ
langage. A performances comparison study was done between both
firmwares. This performances study show good execution speed and
low computational burden. These results encourage to develop simple
predictive algorithms to be programmed in industrial standard hardware.
The main features of the proposed framework are illustrated
through two examples and compared with the anti windup PID
controller.
Abstract: Intelligent traffic surveillance technology is an issue in
the field of traffic data analysis. Therefore, we need the technology to
detect moving objects in real-time while there are variations in background and natural light. In this paper, we proposed a Weighted-Center Surround Difference
method for object detection in outdoor environments. The proposed system detects objects using the saliency map that is obtained by
analyzing the weight of each layers of Gaussian pyramid. In order to validate the effectiveness of our system, we implemented the proposed
method using a digital signal processor, TMS320DM6437.
Experimental results show that blurred noisy around objects was effectively eliminated and the object detection accuracy is improved.