Design of a 5-Joint Mechanical Arm with User-Friendly Control Program

This paper describes the design concepts and implementation of a 5-Joint mechanical arm for a rescue robot named CEO Mission II. The multi-joint arm is a five degree of freedom mechanical arm with a four bar linkage, which can be stretched to 125 cm. long. It is controlled by a teleoperator via the user-friendly control and monitoring GUI program. With Inverse Kinematics principle, we developed the method to control the servo angles of all arm joints to get the desired tip position. By clicking the determined tip position or dragging the tip of the mechanical arm on the computer screen to the desired target point, the robot will compute and move its multi-joint arm to the pose as seen on the GUI screen. The angles of each joint are calculated and sent to all joint servos simultaneously in order to move the mechanical arm to the desired pose at once. The operator can also use a joystick to control the movement of this mechanical arm and the locomotion of the robot. Many sensors are installed at the tip of this mechanical arm for surveillance from the high level and getting the vital signs of victims easier and faster in the urban search and rescue tasks. It works very effectively and easy to control. This mechanical arm and its software were developed as a part of the CEO Mission II Rescue Robot that won the First Runner Up award and the Best Technique award from the Thailand Rescue Robot Championship 2006. It is a low cost, simple, but functioning 5-Jiont mechanical arm which is built from scratch, and controlled via wireless LAN 802.11b/g. This 5-Jiont mechanical arm hardware concept and its software can also be used as the basic mechatronics to many real applications.

FPGA Implementation of the “PYRAMIDS“ Block Cipher

The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.

Spacecraft Neural Network Control System Design using FPGA

Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.

Hardware Prototyping of an Efficient Encryption Engine

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively.

FPGA Based Longitudinal and Lateral Controller Implementation for a Small UAV

This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in FPGA, using its parallel processing capabilities. Attitude controller is designed in MATLAB/Simulink environment. The discrete version of this controller is implemented using pipelining followed by retiming, to reduce the critical path and thereby clock period of the controller datapath. Pipelined, retimed, parallel PID controller implementation is done using rapidprototyping and testing efficient development tool of “system generator", which has been developed by Xilinx for FPGA implementation. The improved timing performance enables the controller to react abruptly to any changes made to the attitudes of UAV.

Low-MAC FEC Controller for JPEG2000 Image Transmission Over IEEE 802.15.4

In this paper, we propose the low-MAC FEC controller for practical implementation of JPEG2000 image transmission using IEEE 802.15.4. The proposed low-MAC FEC controller has very small HW size and spends little computation to estimate channel state. Because of this advantage, it is acceptable to apply IEEE 802.15.4 which has to operate more than 1 year with battery. For the image transmission, we integrate the low-MAC FEC controller and RCPC coder in sensor node of LR-WPAN. The modified sensor node has increase of 3% hardware size than conventional zigbee sensor node.

Low Power and Less Area Architecture for Integer Motion Estimation

Full search block matching algorithm is widely used for hardware implementation of motion estimators in video compression algorithms. In this paper we are proposing a new architecture, which consists of a 2D parallel processing unit and a 1D unit both working in parallel. The proposed architecture reduces both data access power and computational power which are the main causes of power consumption in integer motion estimation. It also completes the operations with nearly the same number of clock cycles as compared to a 2D systolic array architecture. In this work sum of absolute difference (SAD)-the most repeated operation in block matching, is calculated in two steps. The first step is to calculate the SAD for alternate rows by a 2D parallel unit. If the SAD calculated by the parallel unit is less than the stored minimum SAD, the SAD of the remaining rows is calculated by the 1D unit. Early termination, which stops avoidable computations has been achieved with the help of alternate rows method proposed in this paper and by finding a low initial SAD value based on motion vector prediction. Data reuse has been applied to the reference blocks in the same search area which significantly reduced the memory access.

Implementation of Security Algorithms for u-Health Monitoring System

Data security in u-Health system can be an important issue because wireless network is vulnerable to hacking. However, it is not easy to implement a proper security algorithm in an embedded u-health monitoring because of hardware constraints such as low performance, power consumption and limited memory size and etc. To secure data that contain personal and biosignal information, we implemented several security algorithms such as Blowfish, data encryption standard (DES), advanced encryption standard (AES) and Rivest Cipher 4 (RC4) for our u-Health monitoring system and the results were successful. Under the same experimental conditions, we compared these algorithms. RC4 had the fastest execution time. Memory usage was the most efficient for DES. However, considering performance and safety capability, however, we concluded that AES was the most appropriate algorithm for a personal u-Health monitoring system.

Comparison between Skyhook and Minimax Control Strategies for Semi-active Suspension System

This paper describes the development, modeling, and testing of skyhook and MiniMax control strategies of semi-active suspension. The control performances are investigated using Matlab/Simulink [1], with a two-degree-of-freedom quarter car semiactive suspension system model. The comparison and evaluation of control result are made using software-in-the-loop simulation (SILS) method. This paper also outlines the development of a hardware-inthe- loop simulation (HILS) system. The simulation results show that skyhook strategy can significantly reduce the resonant peak of body and provide improvement in vehicle ride comfort. Otherwise, MiniMax strategy can be employed to effectively improve drive safety of vehicle by influencing wheel load. The two strategies can be switched to control semi-active suspension system to fulfill different requirement of vehicle in different stages.

When Construction Material Traders Goes Electronic: Analysis of SMEs in Malaysian Construction Industry

This paper analyzed the perception of e-commerce application services by construction material traders in Malaysia. Five attributes were tested: usability, reputation, trust, privacy and familiarity. Study methodology consists of survey questionnaire and statistical analysis that includes reliability analysis, factor analysis, ANOVA and regression analysis. The respondents were construction material traders, including hardware stores in Klang Valley, Kuala Lumpur. Findings support that usability and familiarity with e-commerce services in Malaysia have insignificant influence on the acceptance of e-commerce application. However, reputation, trust and privacy attributes have significant influence on the choice of e-commerce acceptance by construction material traders. E-commerce applications studied included customer database, e-selling, emarketing, e-payment, e-buying and online advertising. Assumptions are made that traders have basic knowledge and exposure to ICT services. i.e. internet service and computers. Study concludes that reputation, privacy and trust are the three website attributes that influence the acceptance of e-commerce by construction material traders.

A Processor with Dynamically Reconfigurable Circuit for Floating-Point Arithmetic

This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Simulation of Loss-of-Flow Transient in a Radiant Steam Boiler with Relap5/Mod3.2

loss of feedwater accident is one of the frequently sever accidents in steam boiler facilities. It threatens the system structural integrity and generates serious hazards and economic loses. The safety analysis of the thermal installations, based extensively on the numeric simulation. The simulation analysis using realistic computer codes like Relap5/Mod3.2 will help understand steam boiler thermal-hydraulic behavior during normal and abnormal conditions. In this study, we are interested on the evaluation of the radiant steam boiler assessment and response to loss-of-feedwater accident. Pressure, temperature and flow rate profiles are presented in various steam boiler system components. The obtained results demonstrate the importance and capability of the Relap5/Mod3.2 code in the thermal-hydraulic analysis of the steam boiler facilities.

Hardware Description Language Design of Σ-Δ Fractional-N Phase-Locked Loop for Wireless Applications

This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.

Sustainable Water Utilization in Arid Region of Iran by Qanats

To make use of the limited amounts of water in arid region, the Iranians developed man-made underground water channels called qanats (kanats) .In fact, qanats may be considered as the first long-distance water transfer system. Qanats are an ancient water transfer system found in arid regions wherein groundwater from mountainous areas, aquifers and sometimes from rivers, was brought to points of re-emergence such as an oasis, through one or more underground tunnels. The tunnels, many of which were kilometers in length, had designed for slopes to provide gravitational flow. The tunnels allowed water to drain out to the surface by gravity to supply water to lower and flatter agricultural land. Qanats have been an ancient, sustainable system facilitating the harvesting of water for centuries in Iran, and more than 35 additional countries of the world such as India, Arabia, Egypt, North Africa, Spain and even to New world. There are about 22000 qanats in Iran with 274000 kilometers of underground conduits all built by manual labor. The amount of water of the usable qanats of Iran produce is altogether 750 to 1000 cubic meter per second. The longest chain of qanat is situated in Gonabad region in Khorasan province. It is 70 kilometers long. Qanats are renewable water supply systems that have sustained agricultural settlement on the Iranian plateau for millennia. The great advantages of Qanats are no evaporation during transit, little seepage , no raising of the water- table and no pollution in the area surrounding the conduits. Qanat systems have a profound influence on the lives of the water users in Iran, and conform to Iran-s climate. Qanat allows those living in a desert environment adjacent to a mountain watershed to create a large oasis in an otherwise stark environment. This paper explains qanats structure designs, their history, objectives causing their creation, construction materials, locations and their importance in different times, as well as their present sustainable role in Iran.

A 24-Bit, 8.1-MS/s D/A Converter for Audio Baseband Channel Applications

This paper study the high-level modelling and design of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog Converter (DAC) so as to eliminate the in-band Signal-to-Noise- Ratio (SNR) degradation that accompany one channel mismatch in audio signal. The converter combines a cascaded digital signal interpolation, a noise-shaping single loop delta-sigma modulator with a 5-bit quantizer resolution in the final stage. To reduce sensitivity of Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a high pass second order Data Weighted Averaging (R2DWA) is introduced. This paper presents a MATLAB description modelling approach of the proposed DAC architecture with low distortion and swing suppression integrator designs. The ΔΣ Modulator design can be configured as a 3rd-order and allows 24-bit PCM at sampling rate of 64 kHz for Digital Video Disc (DVD) audio application. The modeling approach provides 139.38 dB of dynamic range for a 32 kHz signal band at -1.6 dBFS input signal level.

Hardware Implementations for the ISO/IEC 18033-4:2005 Standard for Stream Ciphers

In this paper the FPGA implementations for four stream ciphers are presented. The two stream ciphers, MUGI and SNOW 2.0 are recently adopted by the International Organization for Standardization ISO/IEC 18033-4:2005 standard. The other two stream ciphers, MICKEY 128 and TRIVIUM have been submitted and are under consideration for the eSTREAM, the ECRYPT (European Network of Excellence for Cryptology) Stream Cipher project. All ciphers were coded using VHDL language. For the hardware implementation, an FPGA device was used. The proposed implementations achieve throughputs range from 166 Mbps for MICKEY 128 to 6080 Mbps for MUGI.

Computing the Loop Bound in Iterative Data Flow Graphs Using Natural Token Flow

Signal processing applications which are iterative in nature are best represented by data flow graphs (DFG). In these applications, the maximum sampling frequency is dependent on the topology of the DFG, the cyclic dependencies in particular. The determination of the iteration bound, which is the reciprocal of the maximum sampling frequency, is critical in the process of hardware implementation of signal processing applications. In this paper, a novel technique to compute the iteration bound is proposed. This technique is different from all previously proposed techniques, in the sense that it is based on the natural flow of tokens into the DFG rather than the topology of the graph. The proposed algorithm has lower run-time complexity than all known algorithms. The performance of the proposed algorithm is illustrated through analytical analysis of the time complexity, as well as through simulation of some benchmark problems.

Groundwater Level Prediction at a Pilot Area in Southeastern Part of the UAE using Shallow Seismic Method

The groundwater is one of the main sources for sustainability in the United Arab Emirates (UAE). Intensive developments in Al-Ain area lead to increase water demand, which consequently reduced the overall groundwater quantity in major aquifers. However, in certain residential areas within Al-Ain, it has been noticed that the groundwater level is rising, for example in Sha-ab Al Askher area. The reasons for the groundwater rising phenomenon are yet to be investigated. In this work, twenty four seismic refraction profiles have been carried out along the study pilot area; as well as field measurement of the groundwater level in a number of available water wells in the area. The processed seismic data indicated the deepest and shallowest groundwater levels are 15m and 2.3 meters respectively. This result is greatly consistent with the proper field measurement of the groundwater level. The minimum detected value may be referred to perched subsurface water which may be associated to the infiltration from the surrounding water bodies such as lakes, and elevated farms. The maximum values indicate the accurate groundwater level within the study area. The findings of this work may be considered as a preliminary help to the decision makers.

A Simplified Single Correlator Rake Receiver for CDMA Communications

This paper presents a single correlator RAKE receiver for direct sequence code division multiple access (DS-CDMA) systems. In conventional RAKE receivers, multiple correlators are used to despread the multipath signals and then to align and combine those signals in a later stage before making a bit decision. The simplified receiver structure presented here uses a single correlator and single code sequence generator to recover the multipaths. Modified Walsh- Hadamard codes are used here for data spreading that provides better uncorrelation properties for the multipath signals. The main advantage of this receiver structure is that it requires only a single correlator and a code generator in contrary to the conventional RAKE receiver concept with multiple correlators. It is shown in results that the proposed receiver achieves better bit error rates in comparison with the conventional one for more than one multipaths.

Improvement over DV-Hop Localization Algorithm for Wireless Sensor Networks

In this paper, we propose improved versions of DVHop algorithm as QDV-Hop algorithm and UDV-Hop algorithm for better localization without the need for additional range measurement hardware. The proposed algorithm focuses on third step of DV-Hop, first error terms from estimated distances between unknown node and anchor nodes is separated and then minimized. In the QDV-Hop algorithm, quadratic programming is used to minimize the error to obtain better localization. However, quadratic programming requires a special optimization tool box that increases computational complexity. On the other hand, UDV-Hop algorithm achieves localization accuracy similar to that of QDV-Hop by solving unconstrained optimization problem that results in solving a system of linear equations without much increase in computational complexity. Simulation results show that the performance of our proposed schemes (QDV-Hop and UDV-Hop) is superior to DV-Hop and DV-Hop based algorithms in all considered scenarios.