Abstract: Signal processing applications which are iterative in
nature are best represented by data flow graphs (DFG). In these
applications, the maximum sampling frequency is dependent on the
topology of the DFG, the cyclic dependencies in particular. The
determination of the iteration bound, which is the reciprocal of the
maximum sampling frequency, is critical in the process of hardware
implementation of signal processing applications. In this paper, a
novel technique to compute the iteration bound is proposed. This
technique is different from all previously proposed techniques, in the
sense that it is based on the natural flow of tokens into the DFG
rather than the topology of the graph. The proposed algorithm has
lower run-time complexity than all known algorithms. The
performance of the proposed algorithm is illustrated through
analytical analysis of the time complexity, as well as through
simulation of some benchmark problems.
Abstract: Formal Specification languages are being widely used
for system specification and testing. Highly critical systems such as
real time systems, avionics, and medical systems are represented
using Formal specification languages. Formal specifications based
testing is mostly performed using black box testing approaches thus
testing only the set of inputs and outputs of the system. The formal
specification language such as VDMµ can be used for white box
testing as they provide enough constructs as any other high level
programming language. In this work, we perform data and control
flow analysis of VDMµ class specifications. The proposed work is
discussed with an example of SavingAccount.