Abstract: The operation of grid-connected inverters necessity a
single-phase phase locked loop (PLL) is proposed in this article to
accurately and quickly estimate and detect the grid phase angle. This
article presents the improvement of a method of phase-locked loop.
The novelty is to generate a method (PLL) of synchronizing the grid
with a Notch filter based on adaptive fuzzy logic for inverter systems
connected to the grid. The performance of the proposed method was
tested under normal and abnormal operating conditions (amplitude,
frequency and phase shift variations). In addition, simulation results
with ISPM software are developed to verify the effectiveness of the
proposed method strategy. Finally, the experimental test will be used
to extract the result and discuss the validity of the proposed algorithm.
Abstract: In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.
Abstract: This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
Abstract: The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.
Abstract: This article deals to describe the simulation
investigation of the digital phase locked loop implemented in
software (SDPLL). SDPLL has been developed for speed drives of an
induction motor in scalar strategy. A drive was implemented and
simulation results are presented to verify the robustness against motor
parameter variation and regulation speed.