LMI Approach to Regularization and Stabilization of Linear Singular Systems: The Discrete-time Case

Sufficient linear matrix inequalities (LMI) conditions for regularization of discrete-time singular systems are given. Then a new class of regularizing stabilizing controllers is discussed. The proposed controllers are the sum of predictive and memoryless state feedbacks. The predictive controller aims to regularizing the singular system while the memoryless state feedback is designed to stabilize the resulting regularized system. A systematic procedure is given to calculate the controller gains through linear matrix inequalities.

Interference Reduction Technique in Multistage Multiuser Detector for DS-CDMA System

This paper presents the results related to the interference reduction technique in multistage multiuser detector for asynchronous DS-CDMA system. To meet the real-time requirements for asynchronous multiuser detection, a bit streaming, cascade architecture is used. An asynchronous multiuser detection involves block-based computations and matrix inversions. The paper covers iterative-based suboptimal schemes that have been studied to decrease the computational complexity, eliminate the need for matrix inversions, decreases the execution time, reduces the memory requirements and uses joint estimation and detection process that gives better performance than the independent parameter estimation method. The stages of the iteration use cascaded and bits processed in a streaming fashion. The simulation has been carried out for asynchronous DS-CDMA system by varying one parameter, i.e., number of users. The simulation result exhibits that system gives optimum bit error rate (BER) at 3rd stage for 15-users.

English Language Learning Strategies Used by University Students: A Case Study of English and Business English Major at Suan Sunandha Rajabhat in Bangkok

The purposes of this research are 1) to study English language learning strategies used by the fourth-year students majoring in English and Business English, 2) to study the English language learning strategies which have an affect on English learning achievement, and 3) to compare the English language learning strategies used by the students majoring in English and Business English. The population and sampling comprise of 139 university students of the Suan Sunandha Rajabhat University. Research instruments are language learning strategies questionnaire which was constructed by the researcher and improved on by three experts and the transcripts that show the results of English learning achievement. The questionnaire includes 1) Language Practice Strategy 2)Memory Strategy 3) Communication Strategy 4)Making an Intelligent Guess or Compensation Strategy 5) Self-discipline in Learning Management Strategy 6) Affective Strategy 7)Self-Monitoring Strategy 8) Self-studySkill Strategy. Statistics used in the study are mean, standard deviation, T-test and One Way ANOVA, Pearson product moment correlation coefficient and Regression Analysis. The results of the findings reveal that the English language learning strategies most frequently used by the students are affective strategy, making an intelligent guess or compensation strategy, self-studyskill strategy and self-monitoring strategy respectively. The aspect of making an intelligent guess or compensation strategy had the most significant affect on English learning achievement. It is found that the English language learning strategies mostly used by the Business English major students and moderately used by the English major students. Their language practice strategies uses were significantly different at the 0.05 level and their communication strategies uses were significantly different at the 0.01 level. In addition, it is found that the poor students and the fair ones most frequently used affective strategy while the good ones most frequently used making an intelligent guess or compensation strategy. KeywordsEnglish language, language learning strategies, English learning achievement, and students majoring in English, Business English. Pranee Pathomchaiwat is an Assistant Professor in Business English Program, Suan Sunandha Rajabhat University, Bangkok, Thailand (e-mail: [email protected]).

Network Reconfiguration for Load Balancing in Distribution System with Distributed Generation and Capacitor Placement

This paper presents an efficient algorithm for optimization of radial distribution systems by a network reconfiguration to balance feeder loads and eliminate overload conditions. The system load-balancing index is used to determine the loading conditions of the system and maximum system loading capacity. The index value has to be minimum in the optimal network reconfiguration of load balancing. A method based on Tabu search algorithm, The Tabu search algorithm is employed to search for the optimal network reconfiguration. The basic idea behind the search is a move from a current solution to its neighborhood by effectively utilizing a memory to provide an efficient search for optimality. It presents low computational effort and is able to find good quality configurations. Simulation results for a radial 69-bus system with distributed generations and capacitors placement. The study results show that the optimal on/off patterns of the switches can be identified to give the best network reconfiguration involving balancing of feeder loads while respecting all the constraints.

MMU Simulation in Hardware Simulator Based-on State Transition Models

Embedded hardware simulator is a valuable computeraided tool for embedded application development. This paper focuses on the ARM926EJ-S MMU, builds state transition models and formally verifies critical properties for the models. The state transition models include loading instruction model, reading data model, and writing data model. The properties of the models are described by CTL specification language, and they are verified in VIS. The results obtained in VIS demonstrate that the critical properties of MMU are satisfied in the state transition models. The correct models can be used to implement the MMU component in our simulator. In the end of this paper, the experimental results show that the MMU can successfully accomplish memory access requests from CPU.

Evaluating the Effectiveness of Memory Overcommit Techniques on KVM-based Hosting Platform

Determining how many virtual machines a Linux host could run can be a challenge. One of tough missions is to find the balance among performance, density and usability. Now KVM hypervisor has become the most popular open source full virtualization solution. It supports several ways of running guests with more memory than host really has. Due to large differences between minimum and maximum guest memory requirements, this paper presents initial results on same-page merging, ballooning and live migration techniques that aims at optimum memory usage on KVM-based cloud platform. Given the design of initial experiments, the results data is worth reference for system administrators. The results from these experiments concluded that each method offers different reliability tradeoff.

Bandwidth, Area Efficient and Target Device Independent DDR SDRAM Controller

The application of the synchronous dynamic random access memory (SDRAM) has gone beyond the scope of personal computers for quite a long time. It comes into hand whenever a big amount of low price and still high speed memory is needed. Most of the newly developed stand alone embedded devices in the field of image, video and sound processing take more and more use of it. The big amount of low price memory has its trade off – the speed. In order to take use of the full potential of the memory, an efficient controller is needed. Efficient stands for maximum random accesses to the memory both for reading and writing and less area after implementation. This paper proposes a target device independent DDR SDRAM pipelined controller and provides performance comparison with available solutions.

A High-Speed and Low-Energy Ternary Content Addressable Memory Design Using Feedback in Match-Line Sense Amplifier

In this paper we present an energy efficient match-line (ML) sensing scheme for high-speed ternary content-addressable memory (TCAM). The proposed scheme isolates the sensing unit of the sense amplifier from the large and variable ML capacitance. It employs feedback in the sense amplifier to successfully detect a match while keeping the ML voltage swing low. This reduced voltage swing results in large energy saving. Simulation performed using 130nm 1.2V CMOS logic shows at least 30% total energy saving in our scheme compared to popular current race (CR) scheme for similar search speed. In terms of speed, dynamic energy, peak power consumption and transistor count our scheme also shows better performance than mismatch-dependant (MD) power allocation technique which also employs feedback in the sense amplifier. Additionally, the implementation of our scheme is simpler than CR or MD scheme because of absence of analog control voltage and programmable delay circuit as have been used in those schemes.

Phase Control Array Synthesis Using Constrained Accelerated Particle Swarm Optimization

In this paper, the phase control antenna array synthesis is presented. The problem is formulated as a constrained optimization problem that imposes nulls with prescribed level while maintaining the sidelobe at a prescribed level. For efficient use of the algorithm memory, compared to the well known Particle Swarm Optimization (PSO), the Accelerated Particle Swarm Optimization (APSO) is used to estimate the phase parameters of the synthesized array. The objective function is formed using a main objective and set of constraints with penalty factors that measure the violation of each feasible solution in the search space to each constraint. In this case the obtained feasible solution is guaranteed to satisfy all the constraints. Simulation results have shown significant performance increases and a decreased randomness in the parameter search space compared to a single objective conventional particle swarm optimization.

Hybrid Approach for Memory Analysis in Windows System

Random Access Memory (RAM) is an important device in computer system. It can represent the snapshot on how the computer has been used by the user. With the growth of its importance, the computer memory has been an issue that has been discussed in digital forensics. A number of tools have been developed to retrieve the information from the memory. However, most of the tools have their limitation in the ability of retrieving the important information from the computer memory. Hence, this paper is aimed to discuss the limitation and the setback for two main techniques such as process signature search and process enumeration. Then, a new hybrid approach will be presented to minimize the setback in both individual techniques. This new approach combines both techniques with the purpose to retrieve the information from the process block and other objects in the computer memory. Nevertheless, the basic theory in address translation for x86 platforms will be demonstrated in this paper.

Memory Leak Detection in Distributed System

Due to memory leaks, often-valuable system memory gets wasted and denied for other processes thereby affecting the computational performance. If an application-s memory usage exceeds virtual memory size, it can leads to system crash. Current memory leak detection techniques for clusters are reactive and display the memory leak information after the execution of the process (they detect memory leak only after it occur). This paper presents a Dynamic Memory Monitoring Agent (DMMA) technique. DMMA framework is a dynamic memory leak detection, that detects the memory leak while application is in execution phase, when memory leak in any process in the cluster is identified by DMMA it gives information to the end users to enable them to take corrective actions and also DMMA submit the affected process to healthy node in the system. Thus provides reliable service to the user. DMMA maintains information about memory consumption of executing processes and based on this information and critical states, DMMA can improve reliability and efficaciousness of cluster computing.

Web Log Mining by an Improved AprioriAll Algorithm

This paper sets forth the possibility and importance about applying Data Mining in Web logs mining and shows some problems in the conventional searching engines. Then it offers an improved algorithm based on the original AprioriAll algorithm which has been used in Web logs mining widely. The new algorithm adds the property of the User ID during the every step of producing the candidate set and every step of scanning the database by which to decide whether an item in the candidate set should be put into the large set which will be used to produce next candidate set. At the meantime, in order to reduce the number of the database scanning, the new algorithm, by using the property of the Apriori algorithm, limits the size of the candidate set in time whenever it is produced. Test results show the improved algorithm has a more lower complexity of time and space, better restrain noise and fit the capacity of memory.

Effect of Preheating Temperature and Chamber Pressure on the Properties of Porous NiTi Alloy Prepared by SHS Technique

The fabrication of porous NiTi shape memory alloys (SMAs) from elemental powder compacts was conducted by selfpropagating high temperature synthesis (SHS). Effects of the preheating temperature and the chamber pressure on the combustion characteristics as well as the final morphology and the composition of products were studied. The samples with porosity between 56.4 and 59.0% under preheating temperature in the range of 200-300°C and Ar-gas chamber pressure of 138 and 201 kPa were obtained. The pore structures were found to be dissimilar only in the samples processed with different preheating temperature. The major phase in the porous product is NiTi with small amounts of secondary phases, NiTi2 and Ni4Ti3. The preheating temperature and the chamber pressure have very little effect on the phase constituent. While the combustion temperature of the sample was notably increased by increasing the preheating temperature, they were slightly changed by varying the chamber pressure.

Humor Roles of Females in a Product Color Matrix

Healthcare providers sometimes use the power of humor as a treatment and therapy for buffering mental health or easing mental disorders because humor can provide relief from distress and conflict. Humor is also very suitable for advertising because of similar benefits. This study carefully examines humor's widespread use in advertising and identifies relationships among humor mechanisms, female depictions, and product types. The purpose is to conceptualize how humor theories can be used not only to successfully define a product as fitting within one of four color categories of the product color matrix, but also to identify compelling contemporary female depictions through humor in ads. The results can offer an idealization for marketing managers and consumers to help them understand how female role depictions can be effectively used with humor in ads. The four propositions developed herein are derived from related literature, through the identification of marketing strategy formulations that achieve product memory enhancement by adopting humor mechanisms properly matched with female role depictions.

Neurogenic Potential of Clitoria ternatea Aqueous Root Extract–A Basis for Enhancing Learning and Memory

The neurogenic potential of many herbal extracts used in Indian medicine is hitherto unknown. Extracts derived from Clitoria ternatea Linn have been used in Indian Ayurvedic system of medicine as an ingredient of “Medhya rasayana", consumed for improving memory and longevity in humans and also in treatment of various neurological disorders. Our earlier experimental studies with oral intubation of Clitoria ternatea aqueous root extract (CTR) had shown significant enhancement of learning and memory in postnatal and young adult Wistar rats. The present study was designed to elucidate the in vitro effects of 200ng/ml of CTR on proliferation, differentiation and growth of anterior subventricular zone neural stem cells (aSVZ NSC-s) derived from prenatal and postnatal rat pups. Results show significant increase in proliferation and growth of neurospheres and increase in the yield of differentiated neurons of aSVZ neural precursor cells (aSVZNPC-s) at 7 days in vitro when treated with 200ng/ml of CTR as compared to age matched control. Results indicate that CTR has growth promoting neurogenic effect on aSVZ neural stem cells and their survival similar to neurotrophic factors like Survivin, Neuregulin 1, FGF-2, BDNF possibly the basis for enhanced learning and memory.

Image Transmission via Iterative Cellular-Turbo System

To compress, improve bit error performance and also enhance 2D images, a new scheme, called Iterative Cellular-Turbo System (IC-TS) is introduced. In IC-TS, the original image is partitioned into 2N quantization levels, where N is denoted as bit planes. Then each of the N-bit-plane is coded by Turbo encoder and transmitted over Additive White Gaussian Noise (AWGN) channel. At the receiver side, bit-planes are re-assembled taking into consideration of neighborhood relationship of pixels in 2-D images. Each of the noisy bit-plane values of the image is evaluated iteratively using IC-TS structure, which is composed of equalization block; Iterative Cellular Image Processing Algorithm (ICIPA) and Turbo decoder. In IC-TS, there is an iterative feedback link between ICIPA and Turbo decoder. ICIPA uses mean and standard deviation of estimated values of each pixel neighborhood. It has extra-ordinary satisfactory results of both Bit Error Rate (BER) and image enhancement performance for less than -1 dB Signal-to-Noise Ratio (SNR) values, compared to traditional turbo coding scheme and 2-D filtering, applied separately. Also, compression can be achieved by using IC-TS systems. In compression, less memory storage is used and data rate is increased up to N-1 times by simply choosing any number of bit slices, sacrificing resolution. Hence, it is concluded that IC-TS system will be a compromising approach in 2-D image transmission, recovery of noisy signals and image compression.

Study of Two Writing Schemes for a Magnetic Tunnel Junction Based On Spin Orbit Torque

MRAM technology provides a combination of fast access time, non-volatility, data retention and endurance. While a growing interest is given to two-terminal Magnetic Tunnel Junctions (MTJ) based on Spin-Transfer Torque (STT) switching as the potential candidate for a universal memory, its reliability is dramatically decreased because of the common writing/reading path. Three-terminal MTJ based on Spin-Orbit Torque (SOT) approach revitalizes the hope of an ideal MRAM. It can overcome the reliability barrier encountered in current two-terminal MTJs by separating the reading and the writing path. In this paper, we study two possible writing schemes for the SOT-MTJ device based on recently fabricated samples. While the first is based on precessional switching, the second requires the presence of permanent magnetic field. Based on an accurate Verilog-A model, we simulate the two writing techniques and we highlight advantages and drawbacks of each one. Using the second technique, pioneering logic circuits based on the three-terminal architecture of the SOT-MTJ described in this work are under development with preliminary attractive results.

Tagging by Combining Rules- Based Method and Memory-Based Learning

Many natural language expressions are ambiguous, and need to draw on other sources of information to be interpreted. Interpretation of the e word تعاون to be considered as a noun or a verb depends on the presence of contextual cues. To interpret words we need to be able to discriminate between different usages. This paper proposes a hybrid of based- rules and a machine learning method for tagging Arabic words. The particularity of Arabic word that may be composed of stem, plus affixes and clitics, a small number of rules dominate the performance (affixes include inflexional markers for tense, gender and number/ clitics include some prepositions, conjunctions and others). Tagging is closely related to the notion of word class used in syntax. This method is based firstly on rules (that considered the post-position, ending of a word, and patterns), and then the anomaly are corrected by adopting a memory-based learning method (MBL). The memory_based learning is an efficient method to integrate various sources of information, and handling exceptional data in natural language processing tasks. Secondly checking the exceptional cases of rules and more information is made available to the learner for treating those exceptional cases. To evaluate the proposed method a number of experiments has been run, and in order, to improve the importance of the various information in learning.

A Novel In-Place Sorting Algorithm with O(n log z) Comparisons and O(n log z) Moves

In-place sorting algorithms play an important role in many fields such as very large database systems, data warehouses, data mining, etc. Such algorithms maximize the size of data that can be processed in main memory without input/output operations. In this paper, a novel in-place sorting algorithm is presented. The algorithm comprises two phases; rearranging the input unsorted array in place, resulting segments that are ordered relative to each other but whose elements are yet to be sorted. The first phase requires linear time, while, in the second phase, elements of each segment are sorted inplace in the order of z log (z), where z is the size of the segment, and O(1) auxiliary storage. The algorithm performs, in the worst case, for an array of size n, an O(n log z) element comparisons and O(n log z) element moves. Further, no auxiliary arithmetic operations with indices are required. Besides these theoretical achievements of this algorithm, it is of practical interest, because of its simplicity. Experimental results also show that it outperforms other in-place sorting algorithms. Finally, the analysis of time and space complexity, and required number of moves are presented, along with the auxiliary storage requirements of the proposed algorithm.

The Hardware Implementation of a Novel Genetic Algorithm

This paper presents a novel genetic algorithm, termed the Optimum Individual Monogenetic Algorithm (OIMGA) and describes its hardware implementation. As the monogenetic strategy retains only the optimum individual, the memory requirement is dramatically reduced and no crossover circuitry is needed, thereby ensuring the requisite silicon area is kept to a minimum. Consequently, depending on application requirements, OIMGA allows the investigation of solutions that warrant either larger GA populations or individuals of greater length. The results given in this paper demonstrate that both the performance of OIMGA and its convergence time are superior to those of existing hardware GA implementations. Local convergence is achieved in OIMGA by retaining elite individuals, while population diversity is ensured by continually searching for the best individuals in fresh regions of the search space.