Abstract: The application of the synchronous dynamic random
access memory (SDRAM) has gone beyond the scope of personal
computers for quite a long time. It comes into hand whenever a big
amount of low price and still high speed memory is needed. Most of
the newly developed stand alone embedded devices in the field of
image, video and sound processing take more and more use of it. The
big amount of low price memory has its trade off – the speed. In
order to take use of the full potential of the memory, an efficient
controller is needed. Efficient stands for maximum random accesses
to the memory both for reading and writing and less area after
implementation. This paper proposes a target device independent
DDR SDRAM pipelined controller and provides performance
comparison with available solutions.