Bandwidth, Area Efficient and Target Device Independent DDR SDRAM Controller

The application of the synchronous dynamic random access memory (SDRAM) has gone beyond the scope of personal computers for quite a long time. It comes into hand whenever a big amount of low price and still high speed memory is needed. Most of the newly developed stand alone embedded devices in the field of image, video and sound processing take more and more use of it. The big amount of low price memory has its trade off – the speed. In order to take use of the full potential of the memory, an efficient controller is needed. Efficient stands for maximum random accesses to the memory both for reading and writing and less area after implementation. This paper proposes a target device independent DDR SDRAM pipelined controller and provides performance comparison with available solutions.

Authors:

• T. Mladenov
• F. Mujahid
• E. Jung
• D. Har

Keywords:

• DDR SDRAM
• controller
• effective implementation

References:

[1] Double Data Rate (DDR) SDRAM Specification, JEDEC STANDARD,
JESD79E, May 2005
[2] The Love/Hate Relationship with DDR SDRAM Controllers, Graham
Allan, MOSAID, www.design-reuse.com.
[3] 128Mb DDR SDRAM, Device Specification, Hynix, April 2006
[4] altdq & altdqs Megafunction, User Guide, Altera, March 2005
[5] PLLs in Stratix II & Stratix II GX Devices, April 2006
[6] How to Use DDR SDRAM, User-s Manual, Document No. E0234E40,
ALPIDA, September 2005
[7] Initialization Sequence for DDR SDRAM, Technical Note, TN-46-08,
Micron.
[8] DDR SDRAM Controller, Reference Design RD1020, Lattice
Semiconductor Corporation, April 2004.
[9] DDR SDRAM Controller Using Virtex-4 FPGA Devices, Oliver
Despaux, Application Note, March 27, 2006.