Abstract: We integrate TiN/Ni/HfO2/Si RRAM cell with a
vertical gate-all-around (GAA) nanowire transistor to achieve
compact 4F2 footprint in a 1T1R configuration. The tip of the Si
nanowire (source of the transistor) serves as bottom electrode of the
memory cell. Fabricated devices with nanowire diameter ~ 50nm
demonstrate ultra-low current/power switching; unipolar switching
with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching
with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the
switching current is found to scale with nanowire diameter making the
architecture promising for future scaling.
Abstract: This paper proposes a method which reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory error correction code. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting codes. The genetic algorithm is employed to solve the non linear power optimization problem. The method is applied to two commonly used SEC-DED codes: standard Hamming and odd column weight Hsiao codes. Experiments were performed to show the performance of the proposed method.
Abstract: Phase transformation temperature is one of the most important parameters for the shape memory alloys (SMAs). The most popular method to determine these phase transformation temperatures is the Differential Scanning Calorimeter (DSC), but due to the limitation of the DSC testing itself, it made it difficult for the finished product which is not in the powder form. A novel method which uses the Universal Testing Machine has been conducted to determine the phase transformation temperatures. The Flexinol wire was applied with force and maintained throughout the experiment and at the same time it was heated up slowly until a temperature of approximately 1000C with direct current. The direct current was then slowly decreased to cool down the temperature of the Flexinol wire. All the phase transformation temperatures for Flexinol wire were obtained. The austenite start at 52.540C and austenite finish at 60.900C, while martensite start at 44.780C and martensite finish at 32.840C.
Abstract: The purpose of this paper is to present a Dynamic
Time Warping technique which reduces significantly the data
processing time and memory size of multi-dimensional time series
sampled by the biometric smart pen device BiSP. The acquisition
device is a novel ballpoint pen equipped with a diversity of sensors
for monitoring the kinematics and dynamics of handwriting
movement. The DTW algorithm has been applied for time series
analysis of five different sensor channels providing pressure,
acceleration and tilt data of the pen generated during handwriting on
a paper pad. But the standard DTW has processing time and memory
space problems which limit its practical use for online handwriting
recognition. To face with this problem the DTW has been applied to
the sum of the five sensor signals after an adequate down-sampling
of the data. Preliminary results have shown that processing time and
memory size could significantly be reduced without deterioration of
performance in single character and word recognition. Further
excellent accuracy in recognition was achieved which is mainly due
to the reduced dynamic time warping RDTW technique and a novel
pen device BiSP.
Abstract: An on-demand routing protocol for wireless ad hoc
networks is one that searches for and attempts to discover a route to
some destination node only when a sending node originates a data
packet addressed to that node. In order to avoid the need for such a
route discovery to be performed before each data packet is sent, such
routing protocols must cache routes previously discovered. This
paper presents an analysis of the effect of intelligent caching in a non
clustered network, using on-demand routing protocols in wireless ad
hoc networks. The analysis carried out is based on the Dynamic
Source Routing protocol (DSR), which operates entirely on-demand.
DSR uses the cache in every node to save the paths that are learnt
during route discovery procedure. In this implementation, caching
these paths only at intermediate nodes and using the paths from these
caches when required is tried. This technique helps in storing more
number of routes that are learnt without erasing the entries in the
cache, to store a new route that is learnt.
The simulation results on DSR have shown that this technique
drastically increases the available memory for caching the routes
discovered without affecting the performance of the DSR routing
protocol in any way, except for a small increase in end to end delay.
Abstract: In this paper, a class of generalized bi-directional associative memory (BAM) neural networks with mixed delays is investigated. On the basis of Lyapunov stability theory and contraction mapping theorem, some new sufficient conditions are established for the existence and uniqueness and globally exponential stability of equilibrium, which generalize and improve the previously known results. One example is given to show the feasibility and effectiveness of our results.
Abstract: In this paper, a system level behavioural model for RF
power amplifier, which exhibits memory effects, and based on multibranch
system is proposed. When higher order terms are included,
the memory polynomial model (MPM) exhibits numerical
instabilities. A set of memory orthogonal polynomial model
(OMPM) is introduced to alleviate the numerical instability problem
associated to MPM model. A data scaling and centring algorithm was
applied to improve the power amplifier modeling accuracy.
Simulation results prove that the numerical instability can be greatly
reduced, as well as the model precision improved with nonlinear
model.
Abstract: The increasing demand for higher data rates in wireless communication systems has led to the more effective and efficient use of all allocated frequency bands. In order to use the whole bandwidth at maximum efficiency, one needs to have RF power amplifiers with a higher linear level and memory-less performance. This is considered to be a major challenge to circuit designers. In this thesis the linearity and memory are studied and examined via the behavior of the intermodulation distortion (IMD). A major source of the in-band distortion can be shown to be influenced by the out-of-band impedances presented at either the input or the output of the device, especially those impedances terminated the low frequency (IF) components. Thus, in order to regulate the in-band distortion, the out of-band distortion must be controllable. These investigations are performed on a 12W LDMOS device characterised at 2.1 GHz within a purpose built, high-power measurement system.
Abstract: Full search block matching algorithm is widely used for hardware implementation of motion estimators in video compression algorithms. In this paper we are proposing a new architecture, which consists of a 2D parallel processing unit and a 1D unit both working in parallel. The proposed architecture reduces both data access power and computational power which are the main causes of power consumption in integer motion estimation. It also completes the operations with nearly the same number of clock cycles as compared to a 2D systolic array architecture. In this work sum of absolute difference (SAD)-the most repeated operation in block matching, is calculated in two steps. The first step is to calculate the SAD for alternate rows by a 2D parallel unit. If the SAD calculated by the parallel unit is less than the stored minimum SAD, the SAD of the remaining rows is calculated by the 1D unit. Early termination, which stops avoidable computations has been achieved with the help of alternate rows method proposed in this paper and by finding a low initial SAD value based on motion vector prediction. Data reuse has been applied to the reference blocks in the same search area which significantly reduced the memory access.
Abstract: Data security in u-Health system can be an important
issue because wireless network is vulnerable to hacking. However, it is
not easy to implement a proper security algorithm in an embedded
u-health monitoring because of hardware constraints such as low
performance, power consumption and limited memory size and etc. To
secure data that contain personal and biosignal information, we
implemented several security algorithms such as Blowfish, data
encryption standard (DES), advanced encryption standard (AES) and
Rivest Cipher 4 (RC4) for our u-Health monitoring system and the
results were successful. Under the same experimental conditions, we
compared these algorithms. RC4 had the fastest execution time.
Memory usage was the most efficient for DES. However, considering
performance and safety capability, however, we concluded that AES
was the most appropriate algorithm for a personal u-Health monitoring
system.
Abstract: One major difficulty that faces developers of
concurrent and distributed software is analysis for concurrency based
faults like deadlocks. Petri nets are used extensively in the
verification of correctness of concurrent programs. ECATNets [2] are
a category of algebraic Petri nets based on a sound combination of
algebraic abstract types and high-level Petri nets. ECATNets have
'sound' and 'complete' semantics because of their integration in
rewriting logic [12] and its programming language Maude [13].
Rewriting logic is considered as one of very powerful logics in terms
of description, verification and programming of concurrent systems.
We proposed in [4] a method for translating Ada-95 tasking
programs to ECATNets formalism (Ada-ECATNet). In this paper,
we show that ECATNets formalism provides a more compact
translation for Ada programs compared to the other approaches based
on simple Petri nets or Colored Petri nets (CPNs). Such translation
doesn-t reduce only the size of program, but reduces also the number
of program states. We show also, how this compact Ada-ECATNet
may be reduced again by applying reduction rules on it. This double
reduction of Ada-ECATNet permits a considerable minimization of
the memory space and run time of corresponding Maude program.
Abstract: In this paper, a class of impulsive BAM fuzzy cellular neural networks with distributed delays and reaction-diffusion terms is formulated and investigated. By employing the delay differential inequality and inequality technique developed by Xu et al., some sufficient conditions ensuring the existence, uniqueness and global exponential stability of equilibrium point for impulsive BAM fuzzy cellular neural networks with distributed delays and reaction-diffusion terms are obtained. In particular, the estimate of the exponential convergence rate is also provided, which depends on system parameters, diffusion effect and impulsive disturbed intention. It is believed that these results are significant and useful for the design and applications of BAM fuzzy cellular neural networks. An example is given to show the effectiveness of the results obtained here.
Abstract: The vehicle fleet of public transportation companies is often equipped with intelligent on-board passenger information systems. A frequently used but time and labor-intensive way for keeping the on-board controllers up-to-date is the manual update using different memory cards (e.g. flash cards) or portable computers. This paper describes a compression algorithm that enables data transmission using low bandwidth wireless radio networks (e.g. GPRS) by minimizing the amount of data traffic. In typical cases it reaches a compression rate of an order of magnitude better than that of the general purpose compressors. Compressed data can be easily expanded by the low-performance controllers, too.
Abstract: In order to answer the general question: “What does a simple agent with a limited life-time require for constructing a useful representation of the environment?" we propose a robot platform including the simplest probabilistic sensory and motor layers. Then we use the platform as a test-bed for evaluation of the navigational capabilities of the robot with different “brains". We claim that a protocognitive behavior is not a consequence of highly sophisticated sensory–motor organs but instead emerges through an increment of the internal complexity and reutilization of the minimal sensory information. We show that the most fundamental robot element, the short-time memory, is essential in obstacle avoidance. However, in the simplest conditions of no obstacles the straightforward memoryless robot is usually superior. We also demonstrate how a low level action planning, involving essentially nonlinear dynamics, provides a considerable gain to the robot performance dynamically changing the robot strategy. Still, however, for very short life time the brainless robot is superior. Accordingly we suggest that small organisms (or agents) with short life-time does not require complex brains and even can benefit from simple brain-like (reflex) structures. To some extend this may mean that controlling blocks of modern robots are too complicated comparative to their life-time and mechanical abilities.
Abstract: Learning programming is difficult for many learners. Some researches have found that the main difficulty relates to cognitive load. Cognitive overload happens in programming due to the nature of the subject which is intrinisicly over-bearing on the working memory. It happens due to the complexity of the subject itself. The problem is made worse by the poor instructional design methodology used in the teaching and learning process. Various efforts have been proposed to reduce the cognitive load, e.g. visualization softwares, part-program method etc. Use of many computer based systems have also been tried to tackle the problem. However, little success has been made to alleviate the problem. More has to be done to overcome this hurdle. This research attempts at understanding how cognitive load can be managed so as to reduce the problem of overloading. We propose a mechanism to measure the cognitive load during pre instruction, post instruction and in instructional stages of learning. This mechanism is used to help the instruction. As the load changes the instruction is made to adapt itself to ensure cognitive viability. This mechanism could be incorporated as a sub domain in the student model of various computer based instructional systems to facilitate the learning of programming.
Abstract: In this study, we examined gender differences in: (1) a
flexible remembering task, that asked for episodic memory decisions
at an item-specific versus category-based level, and (2) the retrieval
specificity of autobiographical memory during free recall.
Differences favouring women were found on both measures.
Furthermore, a significant association was observed, across gender
groups, between level of specificity in the autobiographical memory
interview and sensitivity to gist on the flexible remembering task.
These results suggest that similar cognitive processes may partially
contribute to both the ability for specific autobiographical recall and
the capacity for inhibition of gist-information on the flexible
remembering task.
Abstract: This work aims to reduce the read power consumption
as well as to enhance the stability of the SRAM cell during the read
operation. A new 10-transisor cell is proposed with a new read
scheme to minimize the power consumption within the memory core.
It has separate read and write ports, thus cell read stability is
significantly improved. A 16Kb SRAM macro operating at 1V
supply voltage is demonstrated in 65 nm CMOS process. Its read
power consumption is reduced to 24% of the conventional design.
The new cell also has lower leakage current due to its special bit-line
pre-charge scheme. As a result, it is suitable for low-power mobile
applications where power supply is restricted by the battery.
Abstract: Locality Sensitive Hashing (LSH) is one of the most
promising techniques for solving nearest neighbour search problem in
high dimensional space. Euclidean LSH is the most popular variation
of LSH that has been successfully applied in many multimedia
applications. However, the Euclidean LSH presents limitations that
affect structure and query performances. The main limitation of the
Euclidean LSH is the large memory consumption. In order to achieve
a good accuracy, a large number of hash tables is required. In this
paper, we propose a new hashing algorithm to overcome the storage
space problem and improve query time, while keeping a good
accuracy as similar to that achieved by the original Euclidean LSH.
The Experimental results on a real large-scale dataset show that the
proposed approach achieves good performances and consumes less
memory than the Euclidean LSH.
Abstract: Cellular automata have been used for design of cryptosystems. Recently some secret sharing schemes based on linear memory cellular automata have been introduced which are used for both text and image. In this paper, we illustrate that these secret sharing schemes are vulnerable to dishonest participants- collusion. We propose a cheating model for the secret sharing schemes based on linear memory cellular automata. For this purpose we present a novel uniform model for representation of all secret sharing schemes based on cellular automata. Participants can cheat by means of sending bogus shares or bogus transition rules. Cheaters can cooperate to corrupt a shared secret and compute a cheating value added to it. Honest participants are not aware of cheating and suppose the incorrect secret as the valid one. We prove that cheaters can recover valid secret by removing the cheating value form the corrupted secret. We provide methods of calculating the cheating value.
Abstract: This paper presents a rule-based text- to- speech
(TTS) Synthesis System for Standard Malay, namely SMaTTS. The
proposed system using sinusoidal method and some pre- recorded
wave files in generating speech for the system. The use of phone
database significantly decreases the amount of computer memory
space used, thus making the system very light and embeddable. The
overall system was comprised of two phases the Natural Language
Processing (NLP) that consisted of the high-level processing of text
analysis, phonetic analysis, text normalization and morphophonemic
module. The module was designed specially for SM to overcome
few problems in defining the rules for SM orthography system before
it can be passed to the DSP module. The second phase is the Digital
Signal Processing (DSP) which operated on the low-level process of
the speech waveform generation. A developed an intelligible and
adequately natural sounding formant-based speech synthesis system
with a light and user-friendly Graphical User Interface (GUI) is
introduced. A Standard Malay Language (SM) phoneme set and an
inclusive set of phone database have been constructed carefully for
this phone-based speech synthesizer. By applying the generative
phonology, a comprehensive letter-to-sound (LTS) rules and a
pronunciation lexicon have been invented for SMaTTS. As for the
evaluation tests, a set of Diagnostic Rhyme Test (DRT) word list was
compiled and several experiments have been performed to evaluate
the quality of the synthesized speech by analyzing the Mean Opinion
Score (MOS) obtained. The overall performance of the system as
well as the room for improvements was thoroughly discussed.