Abdul Majid - Journal Author

Shariah Compliance Space Planning for Hotel Room Design

Year: 2015 Volume: 9 Issue: 10 1316 - 1322 Pages

Abstract: This paper illustrates the background of various concepts, approaches, terminologies used to describe the basic framework of an Islamic Hotel Room design. This paper reviews the theoretical views in establishing a suitable and optimum environment for Muslim as well as non-Muslim guests in hotel rooms while according to shariah. It involves a few research methodologies that requires the researcher to study on a few characteristics needed to create more efficient rooms in terms of social interaction, economic growth and other tolerable elements. This paper intends on revealing the elements that are vital and may contribute for hotels in achieving a more conclusive research on space planning for hotel rooms focusing on the shariah and Muslim guests. Malaysia is an Islamic country and has billion of tourists coming over for business and recreational purposes. Therefore, having a righteous environment that best suit this target user is important in terms of generating the economy as well as providing a better understanding to the community on the benefits of applying these qualities in a conventional resort design.

Design and Implementation of a 10-bit SAR ADC with A Programmable Reference

Year: 2014 Volume: 8 Issue: 12 1917 - 1921 Pages

Abstract: This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. The ADC consumed less than 7.5 mW power with a 3 V supply.

Design and Implementation of a 10-bit SAR ADC

Year: 2013 Volume: 7 Issue: 10 1341 - 1344 Pages

Abstract: This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords:
Successive Approximation Register Analog-to- Digital Converter
SAR ADC
Resistive DAC.

Parallel Direct Integration Variable Step Block Method for Solving Large System of Higher Order Ordinary Differential Equations

Year: 2008 Volume: 2 Issue: 4 302 - 306 Pages

Abstract: The aim of this paper is to investigate the performance of the developed two point block method designed for two processors for solving directly non stiff large systems of higher order ordinary differential equations (ODEs). The method calculates the numerical solution at two points simultaneously and produces two new equally spaced solution values within a block and it is possible to assign the computational tasks at each time step to a single processor. The algorithm of the method was developed in C language and the parallel computation was done on a parallel shared memory environment. Numerical results are given to compare the efficiency of the developed method to the sequential timing. For large problems, the parallel implementation produced 1.95 speed-up and 98% efficiency for the two processors.

Support Vector Machine based Intelligent Watermark Decoding for Anticipated Attack

Year: 2008 Volume: 2 Issue: 9 3195 - 3200 Pages

Abstract: In this paper, we present an innovative scheme of blindly extracting message bits from an image distorted by an attack. Support Vector Machine (SVM) is used to nonlinearly classify the bits of the embedded message. Traditionally, a hard decoder is used with the assumption that the underlying modeling of the Discrete Cosine Transform (DCT) coefficients does not appreciably change. In case of an attack, the distribution of the image coefficients is heavily altered. The distribution of the sufficient statistics at the receiving end corresponding to the antipodal signals overlap and a simple hard decoder fails to classify them properly. We are considering message retrieval of antipodal signal as a binary classification problem. Machine learning techniques like SVM is used to retrieve the message, when certain specific class of attacks is most probable. In order to validate SVM based decoding scheme, we have taken Gaussian noise as a test case. We generate a data set using 125 images and 25 different keys. Polynomial kernel of SVM has achieved 100 percent accuracy on test data.

Image Authenticity and Perceptual Optimization via Genetic Algorithm and a Dependence Neighborhood

Year: 2007 Volume: 1 Issue: 2 352 - 357 Pages

Abstract: Information hiding for authenticating and verifying the content integrity of the multimedia has been exploited extensively in the last decade. We propose the idea of using genetic algorithm and non-deterministic dependence by involving the un-watermarkable coefficients for digital image authentication. Genetic algorithm is used to intelligently select coefficients for watermarking in a DCT based image authentication scheme, which implicitly watermark all the un-watermarkable coefficients also, in order to thwart different attacks. Experimental results show that such intelligent selection results in improvement of imperceptibility of the watermarked image, and implicit watermarking of all the coefficients improves security against attacks such as cover-up, vector quantization and transplantation.

High-Resolution 12-Bit Segmented Capacitor DAC in Successive Approximation ADC

Year: 2012 Volume: 6 Issue: 12 1441 - 1444 Pages

Abstract: This paper study the segmented split capacitor Digital-to-Analog Converter (DAC) implemented in a differentialtype 12-bit Successive Approximation Analog-to-Digital Converter (SA-ADC). The series capacitance split array method employed as it reduced the total area of the capacitors required for high resolution DACs. A 12-bit regular binary array structure requires 2049 unit capacitors (Cs) while the split array needs 127 unit Cs. These results in the reduction of the total capacitance and power consumption of the series split array architectures as to regular binary-weighted structures. The paper will show the 12-bit DAC series split capacitor with 4-bit thermometer coded DAC architectures as well as the simulation and measured results.

Keywords:
Successive Approximation Register Analog-to- Digital Converter
SAR ADC
Low voltage ADC.

Nugget Formation during Resistance Spot Welding using Finite Element Model

Year: 2012 Volume: 6 Issue: 7 1173 - 1178 Pages

Abstract: Resistance spot welding process comprises of electric, thermal and mechanical phenomenon, which makes this process complex and highly non-linear and thus, it becomes difficult to model it. In order to obtain good weld nugget during spot welding, hit and trial welds are usually done which is very costly. Therefore the numerical simulation research has been conducted to understand the whole process. In this paper three different cases were analyzed by varying the tip contact area and it was observed that, with the variation of tip contact area the nugget formation at the faying surface is affected. The tip contact area of the welding electrode becomes large with long welding cycles. Therefore in order to maintain consistency of nugget formation during the welding process, the current compensation in control feedback is required. If the contact area of the welding electrode tip is reduced, a large amount of current flows through the faying surface, as a result of which sputtering occurs.

Development of a RAM Simulation Model for Acid Gas Removal System

Year: 2011 Volume: 5 Issue: 12 2594 - 2597 Pages

Abstract: A reliability, availability and maintainability (RAM) model has been built for acid gas removal plant for system analysis that will play an important role in any process modifications, if required, for achieving its optimum performance. Due to the complexity of the plant, the model was based on a Reliability Block Diagram (RBD) with a Monte Carlo simulation engine. The model has been validated against actual plant data as well as local expert opinions, resulting in an acceptable simulation model. The results from the model showed that the operation and maintenance can be further improved, resulting in reduction of the annual production loss.

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