Abstract: This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.
Abstract: In Image processing the Image compression can improve
the performance of the digital systems by reducing the cost and
time in image storage and transmission without significant reduction
of the Image quality. This paper describes hardware architecture of
low complexity Discrete Cosine Transform (DCT) architecture for
image compression[6]. In this DCT architecture, common computations
are identified and shared to remove redundant computations
in DCT matrix operation. Vector processing is a method used for
implementation of DCT. This reduction in computational complexity
of 2D DCT reduces power consumption. The 2D DCT is performed
on 8x8 matrix using two 1-Dimensional Discrete cosine transform
blocks and a transposition memory [7]. Inverse discrete cosine
transform (IDCT) is performed to obtain the image matrix and
reconstruct the original image. The proposed image compression
algorithm is comprehended using MATLAB code. The VLSI design
of the architecture is implemented Using Verilog HDL. The proposed
hardware architecture for image compression employing DCT was
synthesized using RTL complier and it was mapped using 180nm
standard cells. . The Simulation is done using Modelsim. The
simulation results from MATLAB and Verilog HDL are compared.
Detailed analysis for power and area was done using RTL compiler
from CADENCE. Power consumption of DCT core is reduced to
1.027mW with minimum area[1].
Abstract: Recently, the health of retired National Football
League players, particularly lineman has been investigated. A number of studies have reported increased cardiometabolic risk, premature ardiovascular disease and incidence of type 2 diabetes. Rugby union players have somatotypes very similar
to National Football league players which suggest that rugby players may have similar health risks. The International Golden Oldies World Rugby Festival (GORF) provided a
unique opportunity to investigate the demographics of veteran rugby players. METHODOLOGIES: A cross-sectional, observational study was completed using an online web-based
questionnaire that consisted of medical history and
physiological measures. Data analysis was completed using a one sample t-test (50yrs) and Chi-square test. RESULTS: A total of 216 veteran rugby competitors
(response rate = 6.8%) representing 10 countries, aged 35-72 yrs (mean 51.2, S.D. ±8.0), participated in the online survey. As a group, the incidence of current smokers was low at 8.8%
(avg 72.4 cigs/wk) whilst the percentage consuming alcohol
was high (93.1% (avg 11.2 drinks/wk). Competitors reported
the following top six chronic diseases/disorders; hypertension
(18.6%), arthritis (OA/RA, 11.5%), asthma (9.3%),
hyperlipidemia (8.2%), diabetes (all types, 7.5%) and gout (6%), there were significant differences between groups with
regard to cancer (all types) and migraines. When compared to
the Australian general population (Australian Bureau of Statistics data, n=18,000), GORF competitors had a
Climstein Mike, Walsh Joe (corresponding author) and Burke Stephen
School of Exercise Science, Australian Catholic University, 25A Barker Road,
Strathfield, Sydney, NSW, 2016, Australia (e-mail:
[email protected], [email protected],
[email protected]).
John Best is with Orthosports, 160 Belmore Rd., Randwick, Sydney,NSW
2031, Australia (e-mail: [email protected]).
Heazlewood, Ian Timothy is with School of Environmental and Life
Sciences, Faculty Education, Health and Science, Charles Darwin University,
Precinct Yellow Building 2, Charles Darwin University, NT 0909, Australia
(e-mail: [email protected]).
Kettunen Jyrki Arcada University of Applied Sciences, Jan-Magnus
Janssonin aukio 1, FI-00550, Helsinki, Finland (e-mail:
[email protected]).
Adams Kent is with California State University Monterey Bay, Kinesiology Department, 100 Campus Center, Seaside, CA., 93955, USA (email: [email protected]).
DeBeliso Mark is with Department of Physical Education and Human
Performance, Southern Utah University, 351 West University Blvd, Cedar
City, Utah, USA (e-mail: [email protected]).
significantly lower incidence of anxiety (p
Abstract: According to the density of the chips, designers are
trying to put so any facilities of computational and storage on single
chips. Along with the complexity of computational and storage
circuits, the designing, testing and debugging become more and more
complex and expensive. So, hardware design will be built by using
very high speed hardware description language, which is more
efficient and cost effective. This paper will focus on the
implementation of 32-bit ALU design based on Verilog hardware
description language. Adder and subtracter operate correctly on both
unsigned and positive numbers. In ALU, addition takes most of the
time if it uses the ripple-carry adder. The general strategy for
designing fast adders is to reduce the time required to form carry
signals. Adders that use this principle are called carry look- ahead
adder. The carry look-ahead adder is to be designed with combination
of 4-bit adders. The syntax of Verilog HDL is similar to the C
programming language. This paper proposes a unified approach to
ALU design in which both simulation and formal verification can
co-exist.
Abstract: In MPEG and H.26x standards, to eliminate the
temporal redundancy we use motion estimation. Given that the
motion estimation stage is very complex in terms of computational
effort, a hardware implementation on a re-configurable circuit is
crucial for the requirements of different real time multimedia
applications. In this paper, we present hardware architecture for
motion estimation based on "Full Search Block Matching" (FSBM)
algorithm. This architecture presents minimum latency, maximum
throughput, full utilization of hardware resources such as embedded
memory blocks, and combining both pipelining and parallel
processing techniques. Our design is described in VHDL language,
verified by simulation and implemented in a Stratix II
EP2S130F1020C4 FPGA circuit. The experiment result show that the
optimum operating clock frequency of the proposed design is 89MHz
which achieves 160M pixels/sec.
Abstract: This paper describes the design of a real-time audiorange
digital oscilloscope and its implementation in 90nm CMOS
FPGA platform. The design consists of sample and hold circuits,
A/D conversion, audio and video processing, on-chip RAM, clock
generation and control logic. The design of internal blocks and
modules in 90nm devices in an FPGA is elaborated. Also the key
features and their implementation algorithms are presented.
Finally, the timing waveforms and simulation results are put
forward.
Abstract: Face detection and recognition has many applications
in a variety of fields such as security system, videoconferencing and
identification. Face classification is currently implemented in
software. A hardware implementation allows real-time processing,
but has higher cost and time to-market.
The objective of this work is to implement a classifier based on
neural networks MLP (Multi-layer Perceptron) for face detection.
The MLP is used to classify face and non-face patterns. The systm is
described using C language on a P4 (2.4 Ghz) to extract weight
values. Then a Hardware implementation is achieved using VHDL
based Methodology. We target Xilinx FPGA as the implementation
support.
Abstract: Distributed Computing Systems are usually considered the most suitable model for practical solutions of many parallel algorithms. In this paper an enhanced distributed system is presented to improve the time complexity of Binary Indexed Trees (BIT). The proposed system uses multi-uniform processors with identical architectures and a specially designed distributed memory system. The analysis of this system has shown that it has reduced the time complexity of the read query to O(Log(Log(N))), and the update query to constant complexity, while the naive solution has a time complexity of O(Log(N)) for both queries. The system was implemented and simulated using VHDL and Verilog Hardware Description Languages, with xilinx ISE 10.1, as the development environment and ModelSim 6.1c, similarly as the simulation tool. The simulation has shown that the overhead resulting by the wiring and communication between the system fragments could be fairly neglected, which makes it applicable to practically reach the maximum speed up offered by the proposed model.
Abstract: A wideband 2-1-1 cascaded ΣΔ modulator with a
single-bit quantizer in the two first stages and a 4-bit quantizer in the
final stage is developed. To reduce sensitivity of digital-to-analog
converter (DAC) nonlinearities in the feedback of the last stage,
dynamic element matching (DEM) is introduced. This paper presents
two modelling approaches: The first is MATLAB description and the
second is VHDL-AMS modelling of the proposed architecture and
exposes some high-level-simulation results allowing a behavioural
study. The detail of both ideal and non-ideal behaviour modelling are
presented. Then, the study of the effect of building blocks
nonidealities is presented; especially the influences of nonlinearity,
finite operational amplifier gain, amplifier slew rate limitation and
capacitor mismatch. A VHDL-AMS description presents a good
solution to predict system-s performances and can provide sensitivity
curves giving the impact of nonidealities on the system performance.
Abstract: Model-checking tools such as Symbolic Model Verifier
(SMV) and NuSMV are available for checking hardware designs.
These tools can automatically check the formal legitimacy of a
design. However, NuSMV is too low level for describing a complete
hardware design. It is therefore necessary to translate the system
definition, as designed in a language such as Verilog or VHDL, into
a language such as NuSMV for validation. In this paper, we present
a meta hardware description language, Melasy, that contains a code
generator for existing hardware description languages (HDLs) and
languages for model checking that solve this problem.
Abstract: Type 2 diabetes mellitus (T2DM) is a complex
metabolic disorder that characterized by the presence of high glucose
in blood that cause from insulin resistance and insufficiency due to
deterioration β-cell Langerhans functions. T2DM is commonly
caused by the combination of inherited genetic variations as well as
our own lifestyle. Metallothionein (MT) is a known cysteine-rich
protein responsible in helping zinc homeostasis which is important in
insulin signaling and secretion as well as protection our body from
reactive oxygen species (ROS). MT scavenged ROS and free
radicals in our body happen to be one of the reasons of T2DM and its
complications. The objective of this study was to investigate the
association of MT1A and MT2A polymorphisms between T2DM and
control subjects among Malay populations. This study involved 150
T2DM and 120 Healthy individuals of Malay ethnic with mixed
genders. The genomic DNA was extracted from buccal cells and
amplified for MT1A and MT2A loci; the 347bp and 238bp banding
patterns were respectively produced by mean of the Polymerase
Chain Reaction (PCR). The PCR products were digested with Mlucl
and Tsp451 restriction enzymes respectively and producing
fragments lengths of (158/189/347bp) and (103/135/238bp)
respectively. The ANOVA test was conducted and it shown that there
was a significant difference between diabetic and control subjects for
age, BMI, WHR, SBP, FPG, HBA1C, LDL, TG, TC and family
history with (P0.05). The genotype
frequency for AA, AG and GG of MT1A polymorphisms was 72.7%,
22.7% and 4.7% in cases and 15%, 55% and 30% in control
respectively. As for MT2A, genotype frequency of GG, GC and CC
was 42.7%, 27.3% and 30% in case and 5%, 40% and 55% for
control respectively. Both polymorphisms show significant difference
between two investigated groups with (P=0.000). The Post hoc test
was conducted and shows a significant difference between the
genotypes within each polymorphism (P=0. 000). The MT1A and
MT2A polymorphisms were believed to be the reliable molecular
markers to distinguish the T2DM subjects from healthy individuals in
Malay populations.
Abstract: This article describes design of the 8-bit asynchronous
microcontroller simulation model in VHDL. The model is created in
ISE Foundation design tool and simulated in Modelsim tool. This
model is a simple application example of asynchronous systems
designed in synchronous design tools. The design process of creating
asynchronous system with 4-phase bundled-data protocol and with
matching delays is described in the article. The model is described in
gate-level abstraction.
The simulation waveform of the functional construction is the
result of this article. Described construction covers only the
simulation model. The next step would be creating synthesizable
model to FPGA.
Abstract: A multi-board run-time reconfigurable (MRTR)
system for evolvable hardware (EHW) is introduced with the aim to
implement on hardware the bidirectional incremental evolution (BIE)
method. The main features of this digital intrinsic EHW solution rely
on the multi-board approach, the variable chromosome length
management and the partial configuration of the reconfigurable
circuit. These three features provide a high scalability to the solution.
The design has been written in VHDL with the concern of not being
platform dependant in order to keep a flexibility factor as high as
possible. This solution helps tackling the problem of evolving
complex task on digital configurable support.
Abstract: An efficient architecture for low jitter All Digital
Phase Locked Loop (ADPLL) suitable for high speed SoC
applications is presented in this paper. The ADPLL is designed using
standard cells and described by Hardware Description Language
(HDL). The ADPLL implemented in a 90 nm CMOS process can
operate from 10 to 200 MHz and achieve worst case frequency
acquisition in 14 reference clock cycles. The simulation result shows
that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps
at 100MHz. Since the digitally controlled oscillator (DCO) can
achieve both high resolution and wide frequency range, it can meet
the demands of system-level integration. The proposed ADPLL can
easily be ported to different processes in a short time. Thus, it can
reduce the design time and design complexity of the ADPLL, making
it very suitable for System-on-Chip (SoC) applications.