Effect of Herbicides on Narrow Leaved Weeds and Yield of Wheat (Triticum aestivum L.)

This study was conducted to investigate the efficacy of five herbicides on narrow leaved weeds and growth and yield of wheat. An experiment was conducted at Agronomic Research Farm, University of Agriculture Faisalabad. The experiment was laid out in randomized complete block designee (RCBD) with three replications. Treatments studied were clodinafop (Topic-15 WG) at 37 g a.i. ha-1, clodinafop (Topaz-15 WG) at 45 g a.i. ha-1, fenoxaprop-p-ethyl (Puma Super-75 EW) at 45 g a.i. ha-1, fenoxaprop-p-ethyl (Gramicide-6.9 EW) at 85 g a.i. ha-1, fenoxaprop-p-ethyl (Chinlima-6.9 EW) at 85 g a.i. ha-1 and weedy check. Plots treated with fenoxaprop-p-ethyl (Puma Super-75 EW) at 45 g a.i. ha-1 produced relatively less weed biomass, more plant height, number of spike bearing tillers, number of grains per spike, 1000-grain weight and grain yield (4.20 t ha-1).

Recognition of Isolated Speech Signals using Simplified Statistical Parameters

We present a novel scheme to recognize isolated speech signals using certain statistical parameters derived from those signals. The determination of the statistical estimates is based on extracted signal information rather than the original signal information in order to reduce the computational complexity. Subtle details of these estimates, after extracting the speech signal from ambience noise, are first exploited to segregate the polysyllabic words from the monosyllabic ones. Precise recognition of each distinct word is then carried out by analyzing the histogram, obtained from these information.

Spiral Cuff for Fiber-Diameter Selective VNS

In this paper we present the modeling, design, and experimental testing of a nerve cuff multi-electrode system for diameter-selective vagus nerve stimulation. The multi-electrode system contained ninety-nine platinum electrodes embedded within a self-curling spiral silicone sheet. The electrodes were organized in a matrix having nine parallel groups, each containing eleven electrodes. Preliminary testing of the nerve cuff was performed in an isolated segment of a swinish left cervical vagus nerve. For selective vagus nerve stimulation, precisely defined current quasitrapezoidal, asymmetric and biphasic stimulating pulses were applied to preselected locations along the left vagus segment via appointed group of three electrodes within the cuff. Selective stimulation was obtained by anodal block. However, these pulses may not be safe for a long-term application because of a frequently used high imbalance between the cathodic and anodic part of the stimulating pulse. Preliminary results show that the cuff was capable of exciting A and B-fibres, and, that for a certain range of parameters used in stimulating pulses, the contribution of A-fibres to the CAP was slightly reduced and the contribution of B-fibres was slightly larger. Results also showed that measured CAPs are not greatly influenced by the imbalance between a charge Qc injected in cathodic and Qa in anodic phase of quasitrapezoidal, asymmetric and biphasic pulses.

A 10 Giga VPN Accelerator Board for Trust Channel Security System

This paper proposes a VPN Accelerator Board (VPN-AB), a virtual private network (VPN) protocol designed for trust channel security system (TCSS). TCSS supports safety communication channel between security nodes in internet. It furnishes authentication, confidentiality, integrity, and access control to security node to transmit data packets with IPsec protocol. TCSS consists of internet key exchange block, security association block, and IPsec engine block. The internet key exchange block negotiates crypto algorithm and key used in IPsec engine block. Security Association blocks setting-up and manages security association information. IPsec engine block treats IPsec packets and consists of networking functions for communication. The IPsec engine block should be embodied by H/W and in-line mode transaction for high speed IPsec processing. Our VPN-AB is implemented with high speed security processor that supports many cryptographic algorithms and in-line mode. We evaluate a small TCSS communication environment, and measure a performance of VPN-AB in the environment. The experiment results show that VPN-AB gets a performance throughput of maximum 15.645Gbps when we set the IPsec protocol with 3DES-HMAC-MD5 tunnel mode.

Hardware Implementation of Stack-Based Replacement Algorithms

Block replacement algorithms to increase hit ratio have been extensively used in cache memory management. Among basic replacement schemes, LRU and FIFO have been shown to be effective replacement algorithms in terms of hit rates. In this paper, we introduce a flexible stack-based circuit which can be employed in hardware implementation of both LRU and FIFO policies. We propose a simple and efficient architecture such that stack-based replacement algorithms can be implemented without the drawbacks of the traditional architectures. The stack is modular and hence, a set of stack rows can be cascaded depending on the number of blocks in each cache set. Our circuit can be implemented in conjunction with the cache controller and static/dynamic memories to form a cache system. Experimental results exhibit that our proposed circuit provides an average value of 26% improvement in storage bits and its maximum operating frequency is increased by a factor of two

Research into Concrete Blocks with Waste Glass

In this paper, a parametric experimental study for producing paving blocks using fine and coarse waste glass is presented. Some of the physical and mechanical properties of paving blocks having various levels of fine glass (FG) and coarse glass (CG) replacements with fine aggregate (FA) are investigated. The test results show that the replacement of FG by FA at level of 20% by weight has a significant effect on the compressive strength, flexural strength, splitting tensile strength and abrasion resistance of the paving blocks as compared with the control sample because of puzzolanic nature of FG. The compressive strength, flexural strength, splitting tensile strength and abrasion resistance of the paving block samples in the FG replacement level of 20% are 69%, 90%, 47% and 15 % higher as compared with the control sample respectively. It is reported in the earlier works the replacement of FG by FA at level of 20% by weight suppress the alkali-silica reaction (ASR) in the concrete. The test results show that the FG at level of 20% has a potential to be used in the production of paving blocks. The beneficial effect on these properties of CG replacement with FA is little as compared with FG.

Identification of Industrial Health Using ANN

The customary practice of identifying industrial sickness is a set traditional techniques which rely upon a range of manual monitoring and compilation of financial records. It makes the process tedious, time consuming and often are susceptible to manipulation. Therefore, certain readily available tools are required which can deal with such uncertain situations arising out of industrial sickness. It is more significant for a country like India where the fruits of development are rarely equally distributed. In this paper, we propose an approach based on Artificial Neural Network (ANN) to deal with industrial sickness with specific focus on a few such units taken from a less developed north-east (NE) Indian state like Assam. The proposed system provides decision regarding industrial sickness using eight different parameters which are directly related to the stages of sickness of such units. The mechanism primarily uses certain signals and symptoms of industrial health to decide upon the state of a unit. Specifically, we formulate an ANN based block with data obtained from a few selected units of Assam so that required decisions related to industrial health could be taken. The system thus formulated could become an important part of planning and development. It can also contribute towards computerization of decision support systems related to industrial health and help in better management.

A Pipelined FSBM Hardware Architecture for HTDV-H.26x

In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Effects of Late Sowing on Quality of Coriander (Coriandrum sativum L.)

Coriander is an annual and herbaceous plant, belong to the apiaceae family. This plant is cultivated world widely. It is well known for having medicinal properties. The aim of this experiment was to study seed quality of species grown in Kermanshah conditions. The experiment was carried out in research farm, Campus of Agriculture and Natural Resources, Razi University, Kermanshah, Iran. Coriander (local type) was grown in late spring May (5th and 20th) and Jun (4th and 19th), and plant density (10, 30, 50 and 70 plants m-2) in 2009. The experimental plots were laid out in a factorial according to a randomized complete block design with three replications. The fruits were harvest between 83.5 – 106.5 days after sowing. The essential oil and oil content was extracted by Clevenger and Soxhlet apparatuses, respectively. Results showed that delay at planting date increased the oil content. Also, with the increase at plant density was decreased oil content and essential oil.

A Semi-Fragile Watermarking Scheme for Color Image Authentication

In this paper, a semi-fragile watermarking scheme is proposed for color image authentication. In this particular scheme, the color image is first transformed from RGB to YST color space, suitable for watermarking the color media. Each channel is divided into 4×4 non-overlapping blocks and its each 2×2 sub-block is selected. The embedding space is created by setting the two LSBs of selected sub-block to zero, which will hold the authentication and recovery information. For verification of work authentication and parity bits denoted by 'a' & 'p' are computed for each 2×2 subblock. For recovery, intensity mean of each 2×2 sub-block is computed and encoded upto six to eight bits depending upon the channel selection. The size of sub-block is important for correct localization and fast computation. For watermark distribution 2DTorus Automorphism is implemented using a private key to have a secure mapping of blocks. The perceptibility of watermarked image is quite reasonable both subjectively and objectively. Our scheme is oblivious, correctly localizes the tampering and able to recovery the original work with probability of near one.

Routing Capability and Blocking Analysis of Dynamic ROADM Optical Networks (Category - II) for Dynamic Traffic

Reconfigurable optical add/drop multiplexers (ROADMs) can be classified into three categories based on their underlying switching technologies. Category I consists of a single large optical switch; category II is composed of a number of small optical switches aligned in parallel; and category III has a single optical switch and only one wavelength being added/dropped. In this paper, to evaluate the wavelength-routing capability of ROADMs of category-II in dynamic optical networks,the dynamic traffic models are designed based on Bernoulli, Poisson distributions for smooth and regular types of traffic. Through Analytical and Simulation results, the routing power of cat-II of ROADM networks for two traffic models are determined.

Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA

This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

64 bit Computer Architectures for Space Applications – A study

The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Nonlinear Model Predictive Control for Solid Oxide Fuel Cell System Based On Wiener Model

In this paper, we consider Wiener nonlinear model for solid oxide fuel cell (SOFC). The Wiener model of the SOFC consists of a linear dynamic block and a static output non-linearity followed by the block, in which linear part is approximated by state-space model and the nonlinear part is identified by a polynomial form. To control the SOFC system, we have to consider various view points such as operating conditions, another constraint conditions, change of load current and so on. A change of load current is the significant one of these for good performance of the SOFC system. In order to keep the constant stack terminal voltage by changing load current, the nonlinear model predictive control (MPC) is proposed in this paper. After primary control method is designed to guarantee the fuel utilization as a proper constant, a nonlinear model predictive control based on the Wiener model is developed to control the stack terminal voltage of the SOFC system. Simulation results verify the possibility of the proposed Wiener model and MPC method to control of SOFC system.

An Inductive Coupling Based CMOS Wireless Powering Link for Implantable Biomedical Applications

A closed-loop controlled wireless power transmission circuit block for implantable biomedical applications is described in this paper. The circuit consists of one front-end rectifier, power management sub-block including bandgap reference and low drop-out regulators (LDOs) as well as transmission power detection / feedback circuits. Simulation result shows that the front-end rectifier achieves 80% power efficiency with 750-mV single-end peak-to-peak input voltage and 1.28-V output voltage under load current of 4 mA. The power management block can supply 1.8mA average load current under 1V consuming only 12μW power, which is equivalent to 99.3% power efficiency. The wireless power transmission block described in this paper achieves a maximum power efficiency of 80%. The wireless power transmission circuit block is designed and implemented using UMC 65-nm CMOS/RF process. It occupies 1 mm × 1.2 mm silicon area.

Approximate Solutions to Large Stein Matrix Equations

In the present paper, we propose numerical methods for solving the Stein equation AXC - X - D = 0 where the matrix A is large and sparse. Such problems appear in discrete-time control problems, filtering and image restoration. We consider the case where the matrix D is of full rank and the case where D is factored as a product of two matrices. The proposed methods are Krylov subspace methods based on the block Arnoldi algorithm. We give theoretical results and we report some numerical experiments.

Improvement of Bit-Error-Rate in Optical Fiber Receivers

In this paper, a post processing scheme is suggested for improvement of Bit Error-Rate (BER) in optical fiber transmission receivers. The developed scheme has been tested on optical fiber systems operating with a non-return-to-zero (NRZ) format at transmission rates of up to 10Gbps. The transmission system considered is based on well known transmitters and receivers blocks operating at wavelengths in the region of 1550 nm using a standard single mode fiber. Performance of improved detected signals has been evaluated via the analysis of quality factor and computed bit error rates. Numerical simulations have shown a noticeable improvement of the system BER after implementation of the suggested post processing operation on the detected electrical signals.

Effects of Drought on Yield and Some Yield Components of Chickpea

This research was conducted to determine responses of chickpeas to drought in different periods (early period, late period, no-irrigation, two times irrigation as control). The trial was made in “Randomized Complete Block Design" with three replications on 2010 and 2011 years in Konya-Turkey. Genotypes were consisted from 7 lines of ICARDA, 2 certified lines and 1 local population. The results showed that; as means of years and genotypes, early period stress showed highest (207.47 kg da-1) seed yield and it was followed by control (202.33 kg da-1), late period (144.64 kg da-1) and normal (106.93 kg da-1) stress applications. The genotypes were affected too much by drought and, the lowest seed was taken from non-irrigated plots. As the means of years and stress applications, the highest (196.01 kg da-1) yield was taken from genotype 22255. The reason of yield variation could be derived from different responses of genotypes to drought.

Neural Network Tuned Fuzzy Controller for MIMO System

In this paper, a neural network tuned fuzzy controller is proposed for controlling Multi-Input Multi-Output (MIMO) systems. For the convenience of analysis, the structure of MIMO fuzzy controller is divided into single input single-output (SISO) controllers for controlling each degree of freedom. Secondly, according to the characteristics of the system-s dynamics coupling, an appropriate coupling fuzzy controller is incorporated to improve the performance. The simulation analysis on a two-level mass–spring MIMO vibration system is carried out and results show the effectiveness of the proposed fuzzy controller. The performance though improved, the computational time and memory used is comparatively higher, because it has four fuzzy reasoning blocks and number may increase in case of other MIMO system. Then a fuzzy neural network is designed from a set of input-output training data to reduce the computing burden during implementation. This control strategy can not only simplify the implementation problem of fuzzy control, but also reduce computational time and consume less memory.

High Order Cascade Multibit ΣΔ Modulator for Wide Bandwidth Applications

A wideband 2-1-1 cascaded ΣΔ modulator with a single-bit quantizer in the two first stages and a 4-bit quantizer in the final stage is developed. To reduce sensitivity of digital-to-analog converter (DAC) nonlinearities in the feedback of the last stage, dynamic element matching (DEM) is introduced. This paper presents two modelling approaches: The first is MATLAB description and the second is VHDL-AMS modelling of the proposed architecture and exposes some high-level-simulation results allowing a behavioural study. The detail of both ideal and non-ideal behaviour modelling are presented. Then, the study of the effect of building blocks nonidealities is presented; especially the influences of nonlinearity, finite operational amplifier gain, amplifier slew rate limitation and capacitor mismatch. A VHDL-AMS description presents a good solution to predict system-s performances and can provide sensitivity curves giving the impact of nonidealities on the system performance.