Abstract: In this paper we compare the response of linear and
nonlinear neural network-based prediction schemes in prediction of
received Signal-to-Interference Power Ratio (SIR) in Direct
Sequence Code Division Multiple Access (DS/CDMA) systems. The
nonlinear predictor is Multilayer Perceptron MLP and the linear
predictor is an Adaptive Linear (Adaline) predictor. We solve the
problem of complexity by using the Minimum Mean Squared Error
(MMSE) principle to select the optimal predictors. The optimized
Adaline predictor is compared to optimized MLP by employing
noisy Rayleigh fading signals with 1.8 GHZ carrier frequency in an
urban environment. The results show that the Adaline predictor can
estimates SIR with the same error as MLP when the user has the
velocity of 5 km/h and 60 km/h but by increasing the velocity up-to
120 km/h the mean squared error of MLP is two times more than
Adaline predictor. This makes the Adaline predictor (with lower
complexity) more suitable than MLP for closed-loop power control
where efficient and accurate identification of the time-varying
inverse dynamics of the multi path fading channel is required.
Abstract: A closed-loop controlled wireless power transmission circuit block for implantable biomedical applications is described in this paper. The circuit consists of one front-end rectifier, power management sub-block including bandgap reference and low drop-out regulators (LDOs) as well as transmission power detection / feedback circuits. Simulation result shows that the front-end rectifier achieves 80% power efficiency with 750-mV single-end peak-to-peak input voltage and 1.28-V output voltage under load current of 4 mA. The power management block can supply 1.8mA average load current under 1V consuming only 12μW power, which is equivalent to 99.3% power efficiency. The wireless power transmission block described in this paper achieves a maximum power efficiency of 80%. The wireless power transmission circuit block is designed and implemented using UMC 65-nm CMOS/RF process. It occupies 1 mm × 1.2 mm silicon area.