Abstract: Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.
Abstract: We present a family of data-reusing and affine
projection algorithms. For identification of a noisy linear finite
impulse response channel, a partial knowledge of a channel,
especially noise, can be used to improve the performance of
the adaptive filter. Motivated by this fact, the proposed scheme
incorporates an estimate of a knowledge of noise. A constraint, called
the adaptive noise constraint, estimates an unknown information of
noise. By imposing this constraint on a cost function of data-reusing
and affine projection algorithms, a cost function based on the adaptive
noise constraint and Lagrange multiplier is defined. Minimizing the
new cost function leads to the adaptive noise constrained (ANC)
data-reusing and affine projection algorithms. Experimental results
comparing the proposed schemes to standard data-reusing and affine
projection algorithms clearly indicate their superior performance.
Abstract: An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.
Abstract: In this paper, an Infinite Impulse Response (IIR) filter
has been designed and simulated on an Field Programmable Gate
Arrays (FPGA). The implementation is based on Multiply Add and
Accumulate (MAC) algorithm which uses multiply operations for
design implementation. Parallel Pipelined structure is used to
implement the proposed IIR Filter taking optimal advantage of the
look up table of target device. The designed filter has been
synthesized on Digital Signal Processor (DSP) slice based FPGA to
perform multiplier function of MAC unit. The DSP slices are useful
to enhance the speed performance. The proposed design is simulated
with Matlab, synthesized with Xilinx Synthesis Tool, and
implemented on FPGA devices. The Virtex 5 FPGA based design can
operate at an estimated frequency of 81.5 MHz as compared to 40.5
MHz in case of Spartan 3 ADSP based design. The Virtex 5 based
implementation also consumes less slices and slice flip flops of target
FPGA in comparison to Spartan 3 ADSP based implementation to
provide cost effective solution for signal processing applications.
Abstract: The polymer foil used for manufacturing of
laminated glass members behaves in a viscoelastic manner with
temperature dependance. This contribution aims at incorporating
the time/temperature-dependent behavior of interlayer to our earlier
elastic finite element model for laminated glass beams. The model
is based on a refined beam theory: each layer behaves according
to the finite-strain shear deformable formulation by Reissner and
the adjacent layers are connected via the Lagrange multipliers
ensuring the inter-layer compatibility of a laminated unit. The
time/temperature-dependent behavior of the interlayer is accounted
for by the generalized Maxwell model and by the time-temperature
superposition principle due to the Williams, Landel, and Ferry.
The resulting system is solved by the Newton method with
consistent linearization and the viscoelastic response is determined
incrementally by the exponential algorithm. By comparing the model
predictions against available experimental data, we demonstrate that
the proposed formulation is reliable and accurately reproduces the
behavior of the laminated glass units.
Abstract: Presently, it is necessary to ensure the sustainable
development of passenger and freight transport. Increasing
performance of road freight has had a negative impact to environment
and society. It is therefore necessary to increase the competitiveness
of intermodal transport, which is more environmentally friendly. The
study describes the effectiveness of logistical centers realization for
companies and society and research how the partial internalization of
external costs reflected in the efficient use of these centers and
increase the competitiveness of intermodal transport to road freight.
In our research, we use the method of comparative analysis and
market research to describe the advantages of logistic centers for their
users as well as for society as a whole. Method normal costing is used
for calculation infrastructure and total costs, method of conversion
costing for determine the external costs. We modelled total society
costs for road freight transport and inter modal transport chain (we
assumed that most of the traffic is carried by rail) with different
loading schemes for condition in the Slovak Republic. Our research
has shown that higher utilization of inter modal transport chain do
good not only for society, but for companies providing freight
services too. Increase in use of inter modal transport chain can bring
many benefits to society that do not bring direct immediate financial
return. They often bring the multiplier effects, such as greater use of
environmentally friendly transport mode and reduce the total society
costs.
Abstract: Unmanned Aircraft Systems (UAS) become
indispensable parts of modern airpower as force multiplier. One of
the main advantages of UAS is long endurance. UAS have to take
extra payloads to accomplish different missions but these payloads
decrease endurance of aircraft because of increasing drag. There are
continuing researches to increase the capability of UAS. There are
some vertical thermal air currents, which can cause climb and
increase endurance, in nature. Birds and gliders use thermals to gain
altitude with no effort. UAS have wide wings which can use
thermals like birds and gliders. Thermal regions, which is area of
2000-3000 meter (1 NM), exist all around the world. It is natural and
infinite source. This study analyses if thermal regions can be adopted
and implemented as an assistant tool for UAS route planning. First
and second part of study will contain information about the thermal
regions and current applications about UAS in aviation and climbing
performance with a real example. Continuing parts will analyze the
contribution of thermal regions to UAS endurance. Contribution is
important because planning declaration of UAS navigation rules will
be in 2015.
Abstract: In many communication and signal processing
systems, it is highly desirable to implement an efficient narrow-band
filter that decimate or interpolate the incoming signals. This paper
presents hardware efficient compensated CIC filter over a narrow
band frequency that increases the speed of down sampling by using
multiplierless decimation filters with polyphase FIR filter structure.
The proposed work analyzed the performance of compensated CIC
filter on the bases of the improvement of frequency response with
reduced hardware complexity in terms of no. of adders and
multipliers and produces the filtered results without any alterations.
CIC compensator filter demonstrated that by using compensation
with CIC filter improve the frequency response in passed of interest
26.57% with the reduction in hardware complexity 12.25%
multiplications per input sample (MPIS) and 23.4% additions per
input sample (APIS) w.r.t. FIR filter respectively.
Abstract: Shifted polynomial basis (SPB) is a variation of
polynomial basis representation. SPB has potential for efficient
bit level and digi -level implementations of multiplication over
binary extension fields with subquadratic space complexity. For
efficient implementation of pairing computation with large finite
fields, this paper presents a new SPB multiplication algorithm based
on Karatsuba schemes, and used that to derive a novel scalable
multiplier architecture. Analytical results show that the proposed
multiplier provides a trade-off between space and time complexities.
Our proposed multiplier is modular, regular, and suitable for very
large scale integration (VLSI) implementations. It involves less
area complexity compared to the multipliers based on traditional
decomposition methods. It is therefore, more suitable for efficient
hardware implementation of pairing based cryptography and elliptic
curve cryptography (ECC) in constraint driven applications.
Abstract: This paper presents the implementation of Artificial Bees Colony (ABC) algorithm in solving Directional OverCurrent Relays (DOCRs) coordination problem for near-end faults occurring in fixed network topology. The coordination optimization of DOCRs is formulated as linear programming (LP) problem. The objective function is introduced to minimize the operating time of the associated relay which depends on the time multiplier setting. The proposed technique is to taken as a technique for comparison purpose in order to highlight its superiority. The proposed algorithms have been tested successfully on 8 bus test system. The simulation results demonstrated that the ABC algorithm which has been proved to have good search ability is capable in dealing with constraint optimization problems.
Abstract: In this communication, we have made an attempt to design multiplier-less low-pass finite impulse response (FIR) filter with the aid of various mutation strategies of Differential Evolution (DE) algorithm. Impulse response coefficient of the designed FIR filter has been represented as sums or differences of powers of two. Performance of the proposed filter has been evaluated in terms of its frequency response and associated hardware cost. Supremacy of our approach has been substantiated by comparing our result with many of the existing multiplier-less filter design algorithms of recent interest. It has also been demonstrated that DE-optimized filter outperforms Genetic Algorithm (GA) based design by a large margin. Hardware efficiency of our algorithm has further been validated by implementing those filters on a Field Programmable Gate Array (FPGA) chip.
Abstract: In this article, a new inexact alternating direction method(ADM) is proposed for solving a class of variational inequality problems. At each iteration, the new method firstly solves the resulting subproblems of ADM approximately to generate an temporal point ˜xk, and then the multiplier yk is updated to get the new iterate yk+1. In order to get xk+1, we adopt a new descent direction which is simple compared with the existing prediction-correction type ADMs. For the inexact ADM, the resulting proximal subproblem has closedform solution when the proximal parameter and inexact term are chosen appropriately. We show the efficiency of the inexact ADM numerically by some preliminary numerical experiments.
Abstract: Error correcting codes are used for detection and correction of errors in digital communication system. Error correcting coding is based on appending of redundancy to the information message according to a prescribed algorithm. Reed Solomon codes are part of channel coding and withstand the effect of noise, interference and fading. Galois field arithmetic is used for encoding and decoding reed Solomon codes. Galois field multipliers and linear feedback shift registers are used for encoding the information data block. The design of Reed Solomon encoder is complex because of use of LFSR and Galois field arithmetic. The purpose of this paper is to design and implement Reed Solomon (255, 239) encoder with optimized and lesser number of Galois Field multipliers. Symmetric generator polynomial is used to reduce the number of GF multipliers. To increase the capability toward error correction, convolution interleaving will be used with RS encoder. The Design will be implemented on Xilinx FPGA Spartan II.
Abstract: A silicon photomultiplier (SiPM) was designed, fabricated and characterized. The SiPM was based on SACM (Separation of Absorption, Charge and Multiplication) structure, which was optimized for blue light detection in application of positron emission tomography (PET). The achieved SiPM array has a high geometric fill factor of 64% and a low breakdown voltage of about 22V, while the temperature dependence of breakdown voltage is only 17mV/°C. The gain and photon detection efficiency of the device achieved were also measured under illumination of light at 405nm and 460nm wavelengths. The gain of the device is in the order of 106. The photon detection efficiency up to 60% has been observed under 1.8V overvoltage.
Abstract: The optimal control is one of the possible controllers
for a dynamic system, having a linear quadratic regulator and using
the Pontryagin-s principle or the dynamic programming method .
Stochastic disturbances may affect the coefficients (multiplicative
disturbances) or the equations (additive disturbances), provided that
the shocks are not too great . Nevertheless, this approach encounters
difficulties when uncertainties are very important or when the probability
calculus is of no help with very imprecise data. The fuzzy
logic contributes to a pragmatic solution of such a problem since it
operates on fuzzy numbers. A fuzzy controller acts as an artificial
decision maker that operates in a closed-loop system in real time.
This contribution seeks to explore the tracking problem and control
of dynamic macroeconomic models using a fuzzy learning algorithm.
A two inputs - single output (TISO) fuzzy model is applied to the
linear fluctuation model of Phillips and to the nonlinear growth model
of Goodwin.
Abstract: In the present paper the extreme shear stresses with the corresponding planes are established using the freely available computer tools like the Gnuplot, Sage, R, Python and Octave. In order to support these freely available computer tools, their strong symbolical and graphical abilities are illustrated. The nature of the stationary points obtained by the Method of Lagrangian Multipliers can be determined using freely available computer symbolical tools like Sage. The characters of the stationary points can be explained in the easiest way using freely available computer graphical tools like Gnuplot, Sage, R, Python and Octave. The presented figures improve the understanding of the problem and the obtained solutions for the majority of students of civil or mechanical engineering.
Abstract: A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.
Abstract: the present paper, using the technique of differential subordination, we obtain certain results for analytic functions defined by a multiplier transformation in the open unit disc E = { z : IzI < 1}. We claim that our results extend and generalize the existing results in this particular direction
Abstract: In this paper a new fast simplification method is
presented. Such method realizes Karnough map with large
number of variables. In order to accelerate the operation of the
proposed method, a new approach for fast detection of group
of ones is presented. Such approach implemented in the
frequency domain. The search operation relies on performing
cross correlation in the frequency domain rather than time one.
It is proved mathematically and practically that the number of
computation steps required for the presented method is less
than that needed by conventional cross correlation. Simulation
results using MATLAB confirm the theoretical computations.
Furthermore, a powerful solution for realization of complex
functions is given. The simplified functions are implemented
by using a new desigen for neural networks. Neural networks
are used because they are fault tolerance and as a result they
can recognize signals even with noise or distortion. This is
very useful for logic functions used in data and computer
communications. Moreover, the implemented functions are
realized with minimum amount of components. This is done
by using modular neural nets (MNNs) that divide the input
space into several homogenous regions. Such approach is
applied to implement XOR function, 16 logic functions on one
bit level, and 2-bit digital multiplier. Compared to previous
non- modular designs, a clear reduction in the order of
computations and hardware requirements is achieved.
Abstract: This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from 4×4 to 16×16 blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a 16×16 block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.