On Finite Wordlength Properties of Block-Floating-Point Arithmetic

A special case of floating point data representation is block floating point format where a block of operands are forced to have a joint exponent term. This paper deals with the finite wordlength properties of this data format. The theoretical errors associated with the error model for block floating point quantization process is investigated with the help of error distribution functions. A fast and easy approximation formula for calculating signal-to-noise ratio in quantization to block floating point format is derived. This representation is found to be a useful compromise between fixed point and floating point format due to its acceptable numerical error properties over a wide dynamic range.

Study of Integrated Vehicle Image System Including LDW, FCW, and AFS

The objective of this research is to develop an advanced driver assistance system characterized with the functions of lane departure warning (LDW), forward collision warning (FCW) and adaptive front-lighting system (AFS). The system is mainly configured a CCD/CMOS camera to acquire the images of roadway ahead in association with the analysis made by an image-processing unit concerning the lane ahead and the preceding vehicles. The input image captured by a camera is used to recognize the lane and the preceding vehicle positions by image detection and DROI (Dynamic Range of Interesting) algorithms. Therefore, the system is able to issue real-time auditory and visual outputs of warning when a driver is departing the lane or driving too close to approach the preceding vehicle unwittingly so that the danger could be prevented from occurring. During the nighttime, in addition to the foregoing warning functions, the system is able to control the bending light of headlamp to provide an immediate light illumination when making a turn at a curved lane and adjust the level automatically to reduce the lighting interference against the oncoming vehicles driving in the opposite direction by the curvature of lane and the vanishing point estimations. The experimental results show that the integrated vehicle image system is robust to most environments such as the lane detection and preceding vehicle detection average accuracy performances are both above 90 %.

A Continuous Time Sigma Delta Modulators Using CMOS Current Conveyors

In this paper, a alternative structure method for continuous time sigma delta modulator is presented. In this modulator for implementation of integrators in loop filter second generation current conveyors are employed. The modulator is designed in CMOS technology and features low power consumption (65db), and with 180khZ bandwidth. Simulation results confirm that this design is suitable for data converters.

Current Controlled Current Conveyor (CCCII)and Application using 65nm CMOS Technology

Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso / Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results.

High Dynamic Range Resampling for Software Radio

The classic problem of recovering arbitrary values of a band-limited signal from its samples has an added complication in software radio applications; namely, the resampling calculations inevitably fold aliases of the analog signal back into the original bandwidth. The phenomenon is quantified by the spur-free dynamic range. We demonstrate how a novel application of the Remez (Parks- McClellan) algorithm permits optimal signal recovery and SFDR, far surpassing state-of-the-art resamplers.

A Reconfigurable Processing Element for Cholesky Decomposition and Matrix Inversion

Fixed-point simulation results are used for the performance measure of inverting matrices by Cholesky decomposition. The fixed-point Cholesky decomposition algorithm is implemented using a fixed-point reconfigurable processing element. The reconfigurable processing element provides all mathematical operations required by Cholesky decomposition. The fixed-point word length analysis is based on simulations using different condition numbers and different matrix sizes. Simulation results show that 16 bits word length gives sufficient performance for small matrices with low condition number. Larger matrices and higher condition numbers require more dynamic range for a fixedpoint implementation.

A ±0.5V BiCMOS Class-A Current Conveyor

In this paper, a new BiCMOS CCII and CCCII, capable of operate at ±0.5V and having wide dynamic range with achieved bandwidth of 480MHz and 430MHz respectively have been proposed. The structures have been found to be insensitive to the threshold voltage variations. The proposed circuits are suitable for implementation using 0.25μm BiCMOS technology. Pspice simulations confirm the performance of the proposed structures.

Variable Input Range Continuous-time Switched Current Delta-sigma Analog Digital Converter for RFID CMOS Biosensor Applications

Continuous-time delta-sigma analog digital converter (ADC) for radio frequency identification (RFID) complementary metal oxide semiconductor (CMOS) biosensor has been reported. This delta-sigma ADC is suitable for digital conversion of biosensor signal because of small process variation, and variable input range. As the input range of continuous-time switched current delta-sigma ADC (Dynamic range : 50 dB) can be limited by using current reference, amplification of biosensor signal is unnecessary. The input range is switched to wide input range mode or narrow input range mode by command of current reference. When the narrow input range mode, the input range becomes ± 0.8 V. The measured power consumption is 5 mW and chip area is 0.31 mm^2 using 1.2 um standard CMOS process. Additionally, automatic input range detecting system is proposed because of RFID biosensor applications.

Highly Sensitive Label Free Biosensor for Tumor Necrosis Factor

We present a label-free biosensor based on electrochemical impedance spectroscopy for the detection of proinflammatory cytokine Tumor Necrosis Factor (TNF-α). Secretion of TNF-α has been correlated to the onset of various diseases including rheumatoid arthritis, Crohn-s disease etc. Gold electrodes were patterned on a silicon substrate and self assembled monolayer of dithiobis-succinimidyl propionate was used to develop the biosensor which achieved a detection limit of ~57fM. A linear relationship was also observed between increasing TNF-α concentrations and chargetransfer resistance within a dynamic range of 1pg/ml – 1ng/ml.

A Temperature-Insensitive Wide-Dynamic Range Positive/Negative Full-Wave Rectifier Based on Operational Trasconductance Amplifier using Commercially Available ICs

This paper presents positive and negative full-wave rectifier. The proposed structure is based on OTA using commercially available ICs (LT1228). The features of the proposed circuit are that: it can rectify and amplify voltage signal with controllable output magnitude via input bias current: the output voltage is free from temperature variation. The circuit description merely consists of 1 single ended and 3 fully differential OTAs. The performance of the proposed circuit are investigated though PSpice. They show that the proposed circuit can function as positive/negative full-wave rectifier, where the voltage input wide-dynamic range from -5V to 5V. Furthermore, the output voltage is slightly dependent on the temperature variations.

ML Detection with Symbol Estimation for Nonlinear Distortion of OFDM Signal

In this paper, a new technique of signal detection has been proposed for detecting the orthogonal frequency-division multiplexing (OFDM) signal in the presence of nonlinear distortion.There are several advantages of OFDM communications system.However, one of the existing problems is remain considered as the nonlinear distortion generated by high-power-amplifier at the transmitter end due to the large dynamic range of an OFDM signal. The proposed method is the maximum likelihood detection with the symbol estimation. When the training data are available, the neural network has been used to learn the characteristic of received signal and to estimate the new positions of the transmitted symbol which are provided to the maximum likelihood detector. Resulting in the system performance, the nonlinear distortions of a traveling wave tube amplifier with OFDM signal are considered in this paper.Simulation results of the bit-error-rate performance are obtained with 16-QAM OFDM systems.

Versatile Dual-Mode Class-AB Four-Quadrant Analog Multiplier

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.

A Mobile Multihop Relay Dynamic TDD Scheme for Cellular Networks

In this paper, we present an analytical framework for the evaluation of the uplink performance of multihop cellular networks based on dynamic time division duplex (TDD). New wireless broadband protocols, such as WiMAX, WiBro, and 3G-LTE apply TDD, and mobile communication protocols under standardization (e.g., IEEE802.16j) are investigating mobile multihop relay (MMR) as a future technology. In this paper a novel MMR TDD scheme is presented, where the dynamic range of the frame is shared to traffic resources of asymmetric nature and multihop relaying. The mobile communication channel interference model comprises of inner and co-channel interference (CCI). The performance analysis focuses on the uplink due to the fact that the effects of dynamic resource allocation show significant performance degradation only in the uplink compared to time division multiple access (TDMA) schemes due to CCI [1-3], where the downlink results to be the same or better.The analysis was based on the signal to interference power ratio (SIR) outage probability of dynamic TDD (D-TDD) and TDMA systems,which are the most widespread mobile communication multi-user control techniques. This paper presents the uplink SIR outage probability with multihop results and shows that the dynamic TDD scheme applying MMR can provide a performance improvement compared to single hop applications if executed properly.