Abstract: In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.
Abstract: We discuss the alternative conceptions of students analysing the behaviour of electrical circuits. The present paper aims at, on one hand, studying the misconceptions of 80 elementary pre-service teachers from Quebec in Canada, in relation to the current source in DC circuits. To do this, they completed a two-choice questionnaire (true or false) with justification. Data analysis identifies many conceptual difficulties. For example, their majority considered a battery as a source of constant current: When a circuit composed of battery and resistors is modified, the current supplied by the battery remains unchanged. On the other hand, considering the alternatives conceptions identified we develop a two-tier test about source current. The aim of this two-tier test is to help teachers to diagnose rapidly their students’ misconceptions in order to consider in their teaching.
Abstract: In this paper, a technique is proposed to implement
an artificial voltage-controlled capacitance or inductance which can
replace the well-known varactor diode in many applications. The
technique is based on injecting the current of a voltage-controlled
current source onto a fixed capacitor or inductor. Then, by controlling
the transconductance of the current source by an external bias voltage,
a voltage-controlled capacitive or inductive reactance is obtained.
The proposed voltage-controlled reactance devices can be designed
to work anywhere in the frequency spectrum. Practical circuits for the
proposed voltage-controlled reactances are suggested and simulated.
Abstract: Three similar negative differential resistance (NDR)
profiles with both high peak to valley current density ratio (PVCDR)
value and high peak current density (PCD) value in unity resonant
tunneling electronic circuit (RTEC) element is developed in this paper.
The PCD values and valley current density (VCD) values of the three
NDR curves are all about 3.5 A and 0.8 A, respectively. All PV values
of NDR curves are 0.40 V, 0.82 V, and 1.35 V, respectively. The VV
values are 0.61 V, 1.07 V, and 1.69 V, respectively. All PVCDR
values reach about 4.4 in three NDR curves. The PCD value of 3.5 A
in triple PVCDR RTEC element is better than other resonant
tunneling devices (RTD) elements. The high PVCDR value is
concluded the lower VCD value about 0.8 A. The low VCD value is
achieved by suitable selection of resistors in triple PVCDR RTEC
element. The low PV value less than 1.35 V possesses low power
dispersion in triple PVCDR RTEC element. The designed multiple
value logical level (MVLL) system using triple PVCDR RTEC
element provides equidistant logical level. The logical levels of
MVLL system are about 0.2 V, 0.8 V, 1.5 V, and 2.2 V from low
voltage to high voltage and then 2.2 V, 1.3 V, 0.8 V, and 0.2 V from
high voltage back to low voltage in half cycle of sinusoid wave. The
output level of four levels MVLL system is represented in 0.3 V, 1.1 V,
1.7 V, and 2.6 V, which satisfies the NMP condition of traditional
two-bit system. The remarkable logical characteristic of improved
MVLL system with paralleled capacitor are with four significant
stable logical levels about 220 mV, 223 mV, 228 mV, and 230 mV.
The stability and articulation of logical levels of improved MVLL
system are outstanding. The average holding time of improved MVLL
system is approximately 0.14 μs. The holding time of improved
MVLL system is fourfold than of basic MVLL system. The function of
additional capacitor in the improved MVLL system is successfully
discovered.
Abstract: In this paper, we apply the PQ theory with shunt active power filter in an unbalanced and distorted power system voltage to compensate the perturbations generated by non linear load. The power factor is also improved in the current source. The PLL system is used to extract the fundamental component of the even sequence under conditions mentioned of the power system voltage.
Abstract: The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.
Abstract: The paper deals with the comparison study of
harmonic detection methods for a shunt active power filter. The
%THD and the power factor value at the PCC point after
compensation are considered for the comparison. There are three
harmonic detection methods used in the paper that are synchronous
reference frame method, synchronous detection method, and DQ axis
with Fourier method. In addition, the ideal current source is used to
represent the active power filter by assuming an infinitely fast
controller action of the active power filter. The simulation results
show that the DQ axis with Fourier method provides the minimum
%THD after compensation compared with other methods. However,
the power factor value at the PCC point after compensation is slightly
lower than that of synchronous detection method.
Abstract: A current mirror (CM) based on self cascode MOSFETs low voltage analog and mixed mode structures has been proposed. The proposed CM has high output impedance and can operate at 0.5 V. P-Spice simulations confirm the high performance of this CM with a bandwidth of 6.0 GHz at input current of 100 μA.