Abstract: The designing of charge pump with high gain Op-
Amp is a challenging task for getting faithful response .Design of
high performance phase locked loop require ,a design of high
performance charge pump .We have designed a operational amplifier
for reducing the error caused by high speed glitch in a transistor and
mismatch currents . A separate Op-Amp has designed in 180 nm
CMOS technology by CADENCE VIRTUOSO tool. This paper
describes the design of high performance charge pump for GHz
CMOS PLL targeting orthogonal frequency division multiplexing
(OFDM) application. A high speed low power consumption Op-Amp
with more than 500 MHz bandwidth has designed for increasing the
speed of charge pump in Phase locked loop.
Abstract: The intermittent connectivity modifies the “always
on" network assumption made by all the distributed query processing
systems. In modern- day systems, the absence of network
connectivity is considered as a fault. Since the last upload, it might
not be feasible to transmit all the data accumulated right away over
the available connection. It is possible that vital information may be
delayed excessively when the less important information takes place
of the vital information. Owing to the restricted and uneven
bandwidth, it is vital that the mobile nodes make the most
advantageous use of the connectivity when it arrives. Hence, in order
to select the data that needs to be transmitted first, some sort of data
prioritization is essential. A continuous query processing system for
intermittently connected mobile networks that comprises of a delaytolerant
continuous query processor distributed across the mobile
hosts has been proposed in this paper. In addition, a mechanism for
prioritizing query results has been designed that guarantees enhanced
accuracy and reduced delay. It is illustrated that our architecture
reduces the client power consumption, increases query efficiency by
the extensive simulation results.
Abstract: A 2.4GHz (RF) down conversion Gilbert Cell mixer,
implemented in a 0.18-μm CMOS technology with a 1.8V supply, is
presented. Current bleeding (charge injection) technique has been
used to increase the conversion gain and the linearity of the mixer.
The proposed mixer provides 10.75 dB conversion gain ( C G ) with
14.3mw total power consumption. The IIP3 and 1-dB compression
point of the mixer are 8dbm and -4.6dbm respectively, at 300 MHz
IF frequencies. Comparing the current design against the
conventional mixer design, demonstrates better performance in the
conversion gain, linearity, noise figure and port-to-port isolation.
Abstract: With the widespread growth of applications of
Wireless Sensor Networks (WSNs), the need for reliable security
mechanisms these networks has increased manifold. Many security
solutions have been proposed in the domain of WSN so far. These
solutions are usually based on well-known cryptographic
algorithms.
In this paper, we have made an effort to survey well known
security issues in WSNs and study the behavior of WSN nodes that
perform public key cryptographic operations. We evaluate time
and power consumption of public key cryptography algorithm for
signature and key management by simulation.
Abstract: A wireless sensor network with a large number of tiny sensor nodes can be used as an effective tool for gathering data in various situations. One of the major issues in wireless sensor networks is developing an energy-efficient routing protocol which has a significant impact on the overall lifetime of the sensor network. In this paper, we propose a novel hierarchical with static clustering routing protocol called Energy-Efficient Protocol with Static Clustering (EEPSC). EEPSC, partitions the network into static clusters, eliminates the overhead of dynamic clustering and utilizes temporary-cluster-heads to distribute the energy load among high-power sensor nodes; thus extends network lifetime. We have conducted simulation-based evaluations to compare the performance of EEPSC against Low-Energy Adaptive Clustering Hierarchy (LEACH). Our experiment results show that EEPSC outperforms LEACH in terms of network lifetime and power consumption minimization.
Abstract: Since injection engines have a considerable portion, in
consumption of energy and environmental pollution, using an
alternative source of energy with lower pollutant effects in this
regard is necessary.
Biodiesel fuel is a suitable alternative for gasoline in diesel
engines.
In this research the property of biodiesel, the function and the
pollution effects of diesel engine, when using 100% biodiesel, using
100% gasoline and mixing ratio of both fuels for comparing them,
have been investigated.
The researches have shown, using biodiesel fuel in prevalent
diesel engine, will reduce the pollutants such as Co, half burned
carbohydrate and suspended particles and a little increase in
oxidation will achieve while power consumption, particularly fuel
and thermal efficiency of diesel fuel has the same.
Abstract: Modeling of the dynamic behavior and motion are
renewed interest in the improved tractive performance of an
intelligent air-cushion tracked vehicle (IACTV). This paper presents
a new dynamical model for the forces on the developed small scale
intelligent air-cushion tracked vehicle moving over swamp peat. The
air cushion system partially supports the 25 % of vehicle total weight
in order to make the vehicle ground contact pressure 7 kN/m2. As the
air-cushion support system can adjust automatically on the terrain, so
the vehicle can move over the terrain without any risks. The springdamper
system is used with the vehicle body to control the aircushion
support system on any undulating terrain by making the
system sinusoidal form. Experiments have been carried out to
investigate the relationships among tractive efficiency, slippage,
traction coefficient, load distribution ratio, tractive effort, motion
resistance and power consumption in given terrain conditions.
Experiment and simulation results show that air-cushion system
improves the vehicle performance by keeping traction coefficient of
71% and tractive efficiency of 62% and the developed model can
meet the demand of transport efficiency with the optimal power
consumption.
Abstract: In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.
Abstract: Versatile dual-mode class-AB CMOS four-quadrant
analog multiplier circuit is presented. The dual translinear loops and
current mirrors are the basic building blocks in realization scheme.
This technique provides; wide dynamic range, wide-bandwidth response
and low power consumption. The major advantages of this
approach are; its has single ended inputs; since its input is dual translinear
loop operate in class-AB mode which make this multiplier
configuration interesting for low-power applications; current multiplying,
voltage multiplying, or current and voltage multiplying can
be obtainable with balanced input. The simulation results of versatile
analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth
of about 19MHz, a maximum power consumption of 0.46mW,
and temperature compensated. Operation of versatile analog multiplier
was also confirmed through an experiment using CMOS transistor
array.
Abstract: We demonstrate a 1×4 coarse wavelength
division-multiplexing (CWDM) planar concave grating
multiplexer/demultiplexer and its application in re-configurable
optical add/drop multiplexer (ROADM) system in silicon-on-insulator
substrate. The wavelengths of the demonstrated concave grating
multiplexer align well with the ITU-T standard. We demonstrate a
prototype of ROADM comprising two such concave gratings and four
wide-band thermo-optical MZI switches. Undercut technology which
removes the underneath silicon substrate is adopted in optical switches
in order to minimize the operation power. For all the thermal heaters,
the operation voltage is smaller than 1.5 V, and the switch power is
~2.4 mW. High throughput pseudorandom binary sequence (PRBS)
data transmission with up to 100 Gb/s is demonstrated, showing the
high-performance ROADM functionality.
Abstract: This paper proposes a low-cost reconfigurable
architecture for AES algorithm. The proposed architecture separates
SubBytes and MixColumns into two parallel data path, and supports
different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The
throughput and power consumption can be adjusted by changing the
number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K
Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the
minimum throughput is 114Mbps while only using 1 S-Box
Abstract: A high-frequency low-power sinusoidal quadrature
oscillator is presented through the use of two 2nd-order low-pass
current-mirror (CM)-based filters, a 1st-order CM low-pass filter and
a CM bilinear transfer function. The technique is relatively simple
based on (i) inherent time constants of current mirrors, i.e. the
internal capacitances and the transconductance of a diode-connected
NMOS, (ii) a simple negative resistance RN formed by a resistor load
RL of a current mirror. Neither external capacitances nor inductances
are required. As a particular example, a 1.9-GHz, 0.45-mW, 2-V
CMOS low-pass-filter-based all-current-mirror sinusoidal quadrature
oscillator is demonstrated. The oscillation frequency (f0) is 1.9 GHz
and is current-tunable over a range of 370 MHz or 21.6 %. The
power consumption is at approximately 0.45 mW. The amplitude
matching and the quadrature phase matching are better than 0.05 dB
and 0.15°, respectively. Total harmonic distortions (THD) are less
than 0.3 %. At 2 MHz offset from the 1.9 GHz, the carrier to noise
ratio (CNR) is 90.01 dBc/Hz whilst the figure of merit called a
normalized carrier-to-noise ratio (CNRnorm) is 153.03 dBc/Hz. The
ratio of the oscillation frequency (f0) to the unity-gain frequency (fT)
of a transistor is 0.25. Comparisons to other approaches are also
included.