Abstract: The experimental and theoretical results of a ZVS
(Zero Voltage Switching) isolated flyback DC-DC converter using
multilayered coreless PCB step down 2:1 transformer are presented.
The performance characteristics of the transformer are shown which
are useful for the parameters extraction. The measured energy
efficiency of the transformer is found to be more than 94% with the
sinusoidal input voltage excitation. The designed flyback converter
has been tested successfully upto the output power level of 10W,
with a switching frequency in the range of 2.7MHz-4.3MHz. The
input voltage of the converter is varied from 25V-40V DC.
Frequency modulation technique is employed by maintaining
constant off time to regulate the output voltage of the converter. The
energy efficiency of the isolated flyback converter circuit under ZVS
condition in the MHz frequency region is found to be approximately
in the range of 72-84%. This paper gives the comparative results in
terms of the energy efficiency of the hard switched and soft switched
flyback converter in the MHz frequency region.
Abstract: In this paper, we are going to determine the threshold levels of adaptive modulation in a burst by burst CDMA system by a suboptimum method so that the above method attempts to increase the average bit per symbol (BPS) rate of transceiver system by switching between the different modulation modes in variable channel condition. In this method, we choose the minimum values of average bit error rate (BER) and maximum values of average BPS on different values of average channel signal to noise ratio (SNR) and then calculate the relative threshold levels of them, so that when the instantaneous SNR increases, a higher order modulation be employed for increasing throughput and vise-versa when the instantaneous SNR decreases, a lower order modulation be employed for improvement of BER. In transmission step, by this adaptive modulation method, in according to comparison between obtained estimation of pilot symbols and a set of above suboptimum threshold levels, above system chooses one of states no transmission, BPSK, 4QAM and square 16QAM for modulation of data. The expected channel in this paper is a slow Rayleigh fading.
Abstract: This paper describes the design and modeling
procedure of a novel 5-phase segment type switched reluctance motor
(ST-SRM) under simultaneous two-phase (bipolar) excitation of
windings. The rotor cores of ST-SRM are embedded in an aluminum
block as well as to improve the performance characteristics. The
magnetic circuit of the produced ST-SRM is constructed so that the
magnetic flux paths are short and exclusive to each phase, thereby
minimizing the commutation switching and eddy current losses in the
laminations. The design and simulation principles presented apply
primarily to conventional SRM and ST-SRM. It is proved that the
novel 5-phase switched reluctance motor under two-phase excitation
is superior among the criteria used in comparison. The purposed
model is particularly well suited for high torque and weight
constrained applications such as automobiles, aerospace and military
applications.
Abstract: This work presents a recursive identification algorithm. This algorithm relates to the identification of closed loop system with Variable Structure Controller. The approach suggested includes two stages. In the first stage a genetic algorithm is used to obtain the parameters of switching function which gives a control signal rich in commutations (i.e. a control signal whose spectral characteristics are closest possible to those of a white noise signal). The second stage consists in the identification of the system parameters by the instrumental variable method and using the optimal switching function parameters obtained with the genetic algorithm. In order to test the validity of this algorithm a simulation example is presented.
Abstract: Active power filter continues to be a powerful tool to control harmonics in power systems thereby enhancing the power quality. This paper presents a fuzzy tuned PID controller based shunt active filter to diminish the harmonics caused by non linear loads like thyristor bridge rectifiers and imbalanced loads. Here Fuzzy controller provides the tuning of PID, based on firing of thyristor bridge rectifiers and variations in input rms current. The shunt APF system is implemented with three phase current controlled Voltage Source Inverter (VSI) and is connected at the point of common coupling for compensating the current harmonics by injecting equal but opposite filter currents. These controllers are capable of controlling dc-side capacitor voltage and estimating reference currents. Hysteresis Current Controller (HCC) is used to generate switching signals for the voltage source inverter. Simulation studies are carried out with non linear loads like thyristor bridge rectifier along with unbalanced loads and the results proved that the APF along with fuzzy tuned PID controller work flawlessly for different firing angles of non linear load.
Abstract: In this paper, a direct torque control - space vector
modulation (DTC-SVM) scheme is presented for a six-phase speed
and voltage sensorless induction motor (IM) drive. The decoupled
torque and stator flux control is achieved based on IM stator flux field orientation. The rotor speed is detected by on-line estimating of
the rotor angular slip speed and stator vector flux speed. In addition, a simple method is introduced to estimate the stator resistance.
Moreover in this control scheme the voltage sensors are eliminated
and actual motor phase voltages are approximated by using PWM
inverter switching times and the dc link voltage. Finally, some simulation and experimental results are presented to verify the
effectiveness and capability of the proposed control scheme.
Abstract: Implemented 5-bit 125-MS/s successive
approximation register (SAR) analog to digital converter (ADC) on
FPGA is presented in this paper.The design and modeling of a high
performance SAR analog to digital converter are based on monotonic
capacitor switching procedure algorithm .Spartan 3 FPGA is chosen
for implementing SAR analog to digital converter algorithm. SAR
VHDL program writes in Xilinx and modelsim uses for showing
results.
Abstract: In this paper, half bridge DC-DC converters with
transformer isolation presented in the literature are analyzed for highcurrent
and low-voltage applications under the same operation
conditions, and compared in terms of losses and efficiency. The
conventional and improved half-bridge DC-DC converters are
simulated, and current and voltage waveforms are obtained for input
voltage Vdc=500V, output current IO=450A, output voltage VO=38V
and switching frequency fS=20kHz. IGBTs are used as power
semiconductor switches. The power losses of the semiconductor
devices are calculated from current and voltage waveforms. From
simulation results, it is seen that the capacitor switched half bridge
converter has the best efficiency value, and can be preferred at high
power and high frequency applications.
Abstract: This paper proposes a zero-voltage transition (ZVT) PWM synchronous buck converter, which is designed to operate at low output voltage and high efficiency typically required for portable systems. To make the DC-DC converter efficient at lower voltage, synchronous converter is an obvious choice because of lower conduction loss in the diode. The high-side MOSFET is dominated by the switching losses and it is eliminated by the soft switching technique. Additionally, the resonant auxiliary circuit designed is also devoid of the switching losses. The suggested procedure ensures an efficient converter. Theoretical analysis, computer simulation, and experimental results are presented to explain the proposed schemes.
Abstract: Electric vehicle (EV) is one of the effective solutions to
control emission of greenhouses gases in the world. It is of interest
for future transportation due to its sustainability and efficiency by
automotive manufacturers. Various electrical motors have been used
for propulsion system of electric vehicles in last decades. In this
paper brushed DC motor, Induction motor (IM), switched reluctance
motor (SRM) and brushless DC motor (BLDC) are simulated and
compared. BLDC motor is recommended for high performance
electric vehicles. PWM switching technique is implemented for speed
control of BLDC motor. Behavior of different modes of PWM speed
controller of BLDC motor are simulated in MATLAB/SIMULINK.
BLDC motor characteristics are compared and discussed for various
PWM switching modes under normal and inverter fault conditions.
Comparisons and discussions are verified through simulation results.
Abstract: MRAM technology provides a combination of fast
access time, non-volatility, data retention and endurance. While a
growing interest is given to two-terminal Magnetic Tunnel Junctions
(MTJ) based on Spin-Transfer Torque (STT) switching as the
potential candidate for a universal memory, its reliability is
dramatically decreased because of the common writing/reading path.
Three-terminal MTJ based on Spin-Orbit Torque (SOT) approach
revitalizes the hope of an ideal MRAM. It can overcome the
reliability barrier encountered in current two-terminal MTJs by
separating the reading and the writing path. In this paper, we study
two possible writing schemes for the SOT-MTJ device based on
recently fabricated samples. While the first is based on precessional
switching, the second requires the presence of permanent magnetic
field. Based on an accurate Verilog-A model, we simulate the two
writing techniques and we highlight advantages and drawbacks of
each one. Using the second technique, pioneering logic circuits based
on the three-terminal architecture of the SOT-MTJ described in this
work are under development with preliminary attractive results.
Abstract: This paper presents an indirect adaptive stabilization
scheme for first-order continuous-time systems under saturated input
which is described by a sigmoidal function. The singularities are
avoided through a modification scheme for the estimated plant
parameter vector so that its associated Sylvester matrix is guaranteed
to be non-singular and then the estimated plant model is controllable.
The modification mechanism involves the use of a hysteresis
switching function. An alternative hybrid scheme, whose estimated
parameters are updated at sampling instants is also given to solve a
similar adaptive stabilization problem. Such a scheme also uses
hysteresis switching for modification of the parameter estimates so as
to ensure the controllability of the estimated plant model.
Abstract: The performance of a type of fuzzy sliding mode control is researched by considering the nonlinear characteristic of a missile-target interception problem to obtain a robust interception process. The variable boundary layer by using fuzzy logic is proposed to reduce the chattering around the switching surface then is applied to the interception model which was derived. The performances of the sliding mode control with constant and fuzzy boundary layer are compared at the end of the study and the results are evaluated.
Abstract: This paper presents a speed fuzzy sliding mode
controller for a vector controlled induction machine (IM) fed by a
voltage source inverter (PWM).
The sliding mode based fuzzy control method is developed to
achieve fast response, a best disturbance rejection and to maintain a
good decoupling.
The problem with sliding mode control is that there is high
frequency switching around the sliding mode surface. The FSMC is
the combination of the robustness of Sliding Mode Control (SMC)
and the smoothness of Fuzzy Logic (FL). To reduce the torque
fluctuations (chattering), the sign function used in the conventional
SMC is substituted with a fuzzy logic algorithm.
The proposed algorithm was simulated by Matlab/Simulink
software and simulation results show that the performance of the
control scheme is robust and the chattering problem is solved.
Abstract: This paper presents design trade-off and performance impacts of
the amount of pipeline phase of control path signals in a wormhole-switched
network-on-chip (NoC). The numbers of the pipeline phase of the control
path vary between two- and one-cycle pipeline phase. The control paths
consist of the routing request paths for output selection and the arbitration
paths for input selection. Data communications between on-chip routers are
implemented synchronously and for quality of service, the inter-router data
transports are controlled by using a link-level congestion control to avoid
lose of data because of an overflow. The trade-off between the area (logic
cell area) and the performance (bandwidth gain) of two proposed NoC router
microarchitectures are presented in this paper. The performance evaluation is
made by using a traffic scenario with different number of workloads under
2D mesh NoC topology using a static routing algorithm. By using a 130-nm
CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz,
resulting in a high speed network link and high router bandwidth capacity
of about 320 Gbit/s. Based on our experiments, the amount of control path
pipeline stages gives more significant impact on the NoC performance than
the impact on the logic area of the NoC router.
Abstract: MultiProtocol Label Switching (MPLS) is an
emerging technology that aims to address many of the existing issues
associated with packet forwarding in today-s Internetworking
environment. It provides a method of forwarding packets at a high
rate of speed by combining the speed and performance of Layer 2
with the scalability and IP intelligence of Layer 3. In a traditional IP
(Internet Protocol) routing network, a router analyzes the destination
IP address contained in the packet header. The router independently
determines the next hop for the packet using the destination IP
address and the interior gateway protocol. This process is repeated at
each hop to deliver the packet to its final destination. In contrast, in
the MPLS forwarding paradigm routers on the edge of the network
(label edge routers) attach labels to packets based on the forwarding
Equivalence class (FEC). Packets are then forwarded through the
MPLS domain, based on their associated FECs , through swapping
the labels by routers in the core of the network called label switch
routers. The act of simply swapping the label instead of referencing
the IP header of the packet in the routing table at each hop provides
a more efficient manner of forwarding packets, which in turn allows
the opportunity for traffic to be forwarded at tremendous speeds and
to have granular control over the path taken by a packet. This paper
deals with the process of MPLS forwarding mechanism,
implementation of MPLS datapath , and test results showing the
performance comparison of MPLS and IP routing. The discussion
will focus primarily on MPLS IP packet networks – by far the
most common application of MPLS today.
Abstract: We propose a decoy-pulse protocol for frequency-coded implementation of B92 quantum key distribution protocol. A direct extension of decoy-pulse method to frequency-coding scheme results in security loss as an eavesdropper can distinguish between signal and decoy pulses by measuring the carrier photon number without affecting other statistics. We overcome this problem by optimizing the ratio of carrier photon number of decoy-to-signal pulse to be as close to unity as possible. In our method the switching between signal and decoy pulses is achieved by changing the amplitude of RF signal as opposed to modulating the intensity of optical signal thus reducing system cost. We find an improvement by a factor of 100 approximately in the key generation rate using decoy-state protocol. We also study the effect of source fluctuation on key rate. Our simulation results show a key generation rate of 1.5×10-4/pulse for link lengths up to 70km. Finally, we discuss the optimum value of average photon number of signal pulse for a given key rate while also optimizing the carrier ratio.
Abstract: Dynamic models of power converters are normally
time-varying because of their switching actions. Several approaches
are applied to analyze the power converters to achieve the timeinvariant
models suitable for system analysis and design via the
classical control theory. The paper presents how to derive dynamic
models of the power system consisting of a three-phase controlled
rectifier feeding an uncontrolled buck converter by using the
combination between the well known techniques called the DQ and
the generalized state-space averaging methods. The intensive timedomain
simulations of the exact topology model are used to support
the accuracies of the reported model. The results show that the
proposed model can provide good accuracies in both transient and
steady-state responses.
Abstract: Direct Torque Control is a control technique in AC
drive systems to obtain high performance torque control. The
conventional DTC drive contains a pair of hysteresis comparators.
DTC drives utilizing hysteresis comparators suffer from high torque
ripple and variable switching frequency. The most common solution
to those problems is to use the space vector depends on the reference
torque and flux. In this Paper The space vector modulation technique
(SVPWM) is applied to 2 level inverter control in the proposed
DTC-based induction motor drive system, thereby dramatically
reducing the torque ripple. Then the controller based on space vector
modulation is designed to be applied in the control of Induction
Motor (IM) with a three-level Inverter. This type of Inverter has
several advantages over the standard two-level VSI, such as a greater
number of levels in the output voltage waveforms, Lower dV/dt, less
harmonic distortion in voltage and current waveforms and lower
switching frequencies. This paper proposes a general SVPWM
algorithm for three-level based on standard two-level SVPWM. The
proposed scheme is described clearly and simulation results are
reported to demonstrate its effectiveness. The entire control scheme is
implemented with Matlab/Simulink.
Abstract: In this paper, Land Marks for Unique Addressing( LMUA) algorithm is develped to generate unique ID for each and every node which leads to the formation of overlapping/Non overlapping clusters based on unique ID. To overcome the draw back of the developed LMUA algorithm, the concept of clustering is introduced. Based on the clustering concept a Land Marks for Unique Addressing and Clustering(LMUAC) Algorithm is developed to construct strictly non-overlapping clusters and classify those nodes in to Cluster Heads, Member Nodes, Gate way nodes and generating the Hierarchical code for the cluster heads to operate in the level one hierarchy for wireless communication switching. The expansion of the existing network can be performed or not without modifying the cost of adding the clusterhead is shown. The developed algorithm shows one way of efficiently constructing the