CMOS Solid-State Nanopore DNA System-Level Sequencing Techniques Enhancement

This paper presents system level CMOS solid-state nanopore techniques enhancement for speedup next generation molecular recording and high throughput channels. This discussion also considers optimum number of base-pair (bp) measurements through channel as an important role to enhance potential read accuracy. Effective power consumption estimation offered suitable range of multi-channel configuration. Nanopore bp extraction model in statistical method could contribute higher read accuracy with longer read-length (200 < read-length). Nanopore ionic current switching with Time Multiplexing (TM) based multichannel readout system contributed hardware savings.

Cognitive Radio Spectrum Management

The emerging Cognitive Radio is combo of both the technologies i.e. Radio dynamics and software technology. It involve wireless system with efficient coding, designing, and making them artificial intelligent to take the decision according to the surrounding environment and adopt themselves accordingly, so as to deliver the best QoS. This is the breakthrough from fixed hardware and fixed utilization of the spectrum. This software-defined approach of research is centralized at user-definition and application driven model, various software method are used for the optimization of the wireless communication. This paper focused on the Spectrum allocation technique using genetic algorithm GA to evolve radio, represented by chromosomes. The chromosomes gene represents the adjustable parameters in given radio and by using GA, evolving over the generations, the optimized set of parameters are evolved, as per the requirement of user and availability of the spectrum, in our prototype the gene consist of 6 different parameters, and the best set of parameters are evolved according to the application need and availability of the spectrum holes and thus maintaining best QoS for user, simultaneously maintaining licensed user rights. The analyzing tool Matlab is used for the performance of the prototype.

Model-Based Automotive Partitioning and Mapping for Embedded Multicore Systems

This paper introduces novel approaches to partitioning and mapping in terms of model-based embedded multicore system engineering and further discusses benefits, industrial relevance and features in common with existing approaches. In order to assess and evaluate results, both approaches have been applied to a real industrial application as well as to various prototypical demonstrative applications, that have been developed and implemented for different purposes. Evaluations show, that such applications improve significantly according to performance, energy efficiency, meeting timing constraints and covering maintaining issues by using the AMALTHEA platform and the implemented approaches. Furthermore, the model-based design provides an open, expandable, platform independent and scalable exchange format between OEMs, suppliers and developers on different levels. Our proposed mechanisms provide meaningful multicore system utilization since load balancing by means of partitioning and mapping is effectively performed with regard to the modeled systems including hardware, software, operating system, scheduling, constraints, configuration and more data.

Enhanced Disk-Based Databases Towards Improved Hybrid In-Memory Systems

In-memory database systems are becoming popular due to the availability and affordability of sufficiently large RAM and processors in modern high-end servers with the capacity to manage large in-memory database transactions. While fast and reliable inmemory systems are still being developed to overcome cache misses, CPU/IO bottlenecks and distributed transaction costs, disk-based data stores still serve as the primary persistence. In addition, with the recent growth in multi-tenancy cloud applications and associated security concerns, many organisations consider the trade-offs and continue to require fast and reliable transaction processing of diskbased database systems as an available choice. For these organizations, the only way of increasing throughput is by improving the performance of disk-based concurrency control. This warrants a hybrid database system with the ability to selectively apply an enhanced disk-based data management within the context of inmemory systems that would help improve overall throughput. The general view is that in-memory systems substantially outperform disk-based systems. We question this assumption and examine how a modified variation of access invariance that we call enhanced memory access, (EMA) can be used to allow very high levels of concurrency in the pre-fetching of data in disk-based systems. We demonstrate how this prefetching in disk-based systems can yield close to in-memory performance, which paves the way for improved hybrid database systems. This paper proposes a novel EMA technique and presents a comparative study between disk-based EMA systems and in-memory systems running on hardware configurations of equivalent power in terms of the number of processors and their speeds. The results of the experiments conducted clearly substantiate that when used in conjunction with all concurrency control mechanisms, EMA can increase the throughput of disk-based systems to levels quite close to those achieved by in-memory system. The promising results of this work show that enhanced disk-based systems facilitate in improving hybrid data management within the broader context of in-memory systems.

Simulation Based VLSI Implementation of Fast Efficient Lossless Image Compression System Using Adjusted Binary Code & Golumb Rice Code

The Simulation based VLSI Implementation of FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression and is implemented in simulation oriented VLSI (Very Large Scale Integrated). To analysis the performance of Lossless image compression and to reduce the image without losing image quality and then implemented in VLSI based FELICS algorithm. In FELICS algorithm, which consists of simplified adjusted binary code for Image compression and these compression image is converted in pixel and then implemented in VLSI domain. This parameter is used to achieve high processing speed and minimize the area and power. The simplified adjusted binary code reduces the number of arithmetic operation and achieved high processing speed. The color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Although VLSI based FELICS Algorithm provides effective solution for hardware architecture design for regular pipelining data flow parallelism with four stages. With two level parallelisms, consecutive pixels can be classified into even and odd samples and the individual hardware engine is dedicated for each one. This method can be further enhanced by multilevel parallelisms.

Design and Implementation of DC-DC Converter with Inc-Cond Algorithm

The most important component affecting the efficiency of photovoltaic power systems are solar panels. In other words, efficiency of these systems are significantly affected due to the being low efficiency of solar panel. Thus, solar panels should be operated under maximum power point conditions through a power converter. In this study, design of boost converter has been carried out with maximum power point tracking (MPPT) algorithm which is incremental conductance (Inc-Cond). By using this algorithm, importance of power converter in MPPT hardware design, impacts of MPPT operation have been shown. It is worth noting that initial operation point is the main criteria for determining the MPPT performance. In addition, it is shown that if value of load resistance is lower than critical value, failure operation is realized. For these analyzes, direct duty control is used for simplifying the control.

High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform

Real time image and video processing is a demand in many computer vision applications, e.g. video surveillance, traffic management and medical imaging. The processing of those video applications requires high computational power. Thus, the optimal solution is the collaboration of CPU and hardware accelerators. In this paper, a Canny edge detection hardware accelerator is proposed. Edge detection is one of the basic building blocks of video and image processing applications. It is a common block in the pre-processing phase of image and video processing pipeline. Our presented approach targets offloading the Canny edge detection algorithm from processing system (PS) to programmable logic (PL) taking the advantage of High Level Synthesis (HLS) tool flow to accelerate the implementation on Zynq platform. The resulting implementation enables up to a 100x performance improvement through hardware acceleration. The CPU utilization drops down and the frame rate jumps to 60 fps of 1080p full HD input video stream.

Individual Actuators of a Car-Like Robot with Back Trailer

This paper presents the hardware implemented and validation for a special system to assist the unprofessional users of car with back trailers. The system consists of two platforms; the front car platform (C) and the trailer platform (T). The main objective is to control the Trailer platform using the actuators found in the front platform (c). The mobility of the platform (C) is investigated and inverse and forward kinematics model is obtained for both platforms (C) and (T).The system is simulated using Matlab M-file and the simulation examples results illustrated the system performance. The system is constructed with a hardware setup for the front and trailer platform. The hardware experimental results and the simulated examples outputs showed the validation of the hardware setup.

Real Time Remote Monitoring and Fault Detection in Wind Turbine

In new energy development, wind power has boomed. It is due to the proliferation of wind parks and their operation in supplying the national electric grid with low cost and clean resources. Hence, there is an increased need to establish a proactive maintenance for wind turbine machines based on remote control and monitoring. That is necessary with a real-time wireless connection in offshore or inaccessible locations while the wired method has many flaws. The objective of this strategy is to prolong wind turbine lifetime and to increase productivity. The hardware of a remote control and monitoring system for wind turbine parks is designed. It takes advantage of GPRS or Wi-Max wireless module to collect data measurements from different wind machine sensors through IP based multi-hop communication. Computer simulations with Proteus ISIS and OPNET software tools have been conducted to evaluate the performance of the studied system. Study findings show that the designed device is suitable for application in a wind park.

Channel Sounding and PAPR Reduction in OFDM for WiMAX Using Software Defined Radio

This paper addresses the reduction of peak to average power ratio (PAPR) for the OFDM in Mobile-WiMAX physical layer (PHY) standard. In the process, the best achievable PAPR of 0 dB is found for the OFDM spectrum using phase modulation technique which avoids the nonlinear distortion. The performance of the WiMAX PHY standard is handled by the software defined radio (SDR) prototype in which GNU Radio and USRP N210 employed as software and hardware platforms respectively. It is also found that BER performance is shown for different coding and different modulation schemes. To empathize wireless propagation in specific environments, a sliding correlator wireless channel sounding system is designed by using SDR testbed.

Application of Hardware Efficient CIC Compensation Filter in Narrow Band Filtering

In many communication and signal processing systems, it is highly desirable to implement an efficient narrow-band filter that decimate or interpolate the incoming signals. This paper presents hardware efficient compensated CIC filter over a narrow band frequency that increases the speed of down sampling by using multiplierless decimation filters with polyphase FIR filter structure. The proposed work analyzed the performance of compensated CIC filter on the bases of the improvement of frequency response with reduced hardware complexity in terms of no. of adders and multipliers and produces the filtered results without any alterations. CIC compensator filter demonstrated that by using compensation with CIC filter improve the frequency response in passed of interest 26.57% with the reduction in hardware complexity 12.25% multiplications per input sample (MPIS) and 23.4% additions per input sample (APIS) w.r.t. FIR filter respectively.

Design and Development of an Innovative Advertisement Display with Flipping Mechanism

Attractive and creative advertisement displays are often in high demand as they are known to have profound impact on the commercial market. In the fast advancement of technology, advertising trend has taken a great leap in attracting more and more demanding consumers. A low-cost and low-power consumption flipping advertisement board has been developed in this paper. The design of the electrical circuit and the controller of the advertisement board are presented. A microcontroller, a Darlington Pair driver and a unipolar stepper motor were used to operate the electrical flipping advertisement board. The proposed system has been implemented and the hardware has been tested to demonstrate the capability of displaying multiple advertisements in a panel.

Lego Mindstorms as a Simulation of Robotic Systems

In this paper we deal with using Lego Mindstorms in simulation of robotic systems with respect to cost reduction. Lego Mindstorms kit contains broad variety of hardware components which are required to simulate, program and test the robotics systems in practice. Algorithm programming went in development environment supplied together with Lego kit as in programming language C# as well. Algorithm following the line, which we dealt with in this paper, uses theoretical findings from area of controlling circuits. PID controller has been chosen as controlling circuit whose individual components were experimentally adjusted for optimal motion of robot tracking the line. Data which are determined to process by algorithm are collected by sensors which scan the interface between black and white surfaces followed by robot. Based on discovered facts Lego Mindstorms can be considered for low-cost and capable kit to simulate real robotics systems.

Conception of a Reliable, Low Cost and Autonomous Explorative Hovercraft

The paper presents actual benefits and drawbacks of a multidirectional autonomous hovercraft conceived with limited resources and designed for indoor exploration. Recent developments in the field have led to the apparition of very powerful automotive systems capable of very high calculation and exploration in complex unknown environments. They usually propose very complex algorithms, high precision/cost sensors and sometimes have heavy calculation consumption with complex data fusion. These systems are usually powerful but have a certain price, and the benefits may not be worth the cost, especially considering their hardware limitations and their power consumption. The present approach is to build a compromise between cost, power consumption and results preciseness.

Searchable Encryption in Cloud Storage

Cloud outsource storage is one of important services in cloud computing. Cloud users upload data to cloud servers to reduce the cost of managing data and maintaining hardware and software. To ensure data confidentiality, users can encrypt their files before uploading them to a cloud system. However, retrieving the target file from the encrypted files exactly is difficult for cloud server. This study proposes a protocol for performing multikeyword searches for encrypted cloud data by applying k-nearest neighbor technology. The protocol ranks the relevance scores of encrypted files and keywords, and prevents cloud servers from learning search keywords submitted by a cloud user. To reduce the costs of file transfer communication, the cloud server returns encrypted files in order of relevance. Moreover, when a cloud user inputs an incorrect keyword and the number of wrong alphabet does not exceed a given threshold; the user still can retrieve the target files from cloud server. In addition, the proposed scheme satisfies security requirements for outsourced data storage.

Design of an Efficient Retimed CIC Compensation Filter

Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improve through high-level architectural transformation in circuit level. Reallocating registers and  relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology, that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter.

Scalable Systolic Multiplier over Binary Extension Fields Based on Two-Level Karatsuba Decomposition

Shifted polynomial basis (SPB) is a variation of polynomial basis representation. SPB has potential for efficient bit level and digi -level implementations of multiplication over binary extension fields with subquadratic space complexity. For efficient implementation of pairing computation with large finite fields, this paper presents a new SPB multiplication algorithm based on Karatsuba schemes, and used that to derive a novel scalable multiplier architecture. Analytical results show that the proposed multiplier provides a trade-off between space and time complexities. Our proposed multiplier is modular, regular, and suitable for very large scale integration (VLSI) implementations. It involves less area complexity compared to the multipliers based on traditional decomposition methods. It is therefore, more suitable for efficient hardware implementation of pairing based cryptography and elliptic curve cryptography (ECC) in constraint driven applications.

Stimulus-Dependent Polyrhythms of Central Pattern Generator Hardware

We have built universal central pattern generator (CPG) hardware by interconnecting Hodgkin-Huxley neurons with reciprocally inhibitory synapses. We investigate the dynamics of neuron oscillations as a function of the time delay between current steps applied to individual neurons. We demonstrate stimulus dependent switching between spiking polyrhythms and map the phase portraits of the neuron oscillations to reveal the basins of attraction of the system. We experimentally study the dependence of the attraction basins on the network parameters: The neuron response time and the strength of inhibitory connections.

Unsupervised Feature Learning by Pre-Route Simulation of Auto-Encoder Behavior Model

This paper describes a cycle accurate simulation results of weight values learned by an auto-encoder behavior model in terms of pre-route simulation. Given the results we visualized the first layer representations with natural images. Many common deep learning threads have focused on learning high-level abstraction of unlabeled raw data by unsupervised feature learning. However, in the process of handling such a huge amount of data, the learning method’s computation complexity and time limited advanced research. These limitations came from the fact these algorithms were computed by using only single core CPUs. For this reason, parallel-based hardware, FPGAs, was seen as a possible solution to overcome these limitations. We adopted and simulated the ready-made auto-encoder to design a behavior model in VerilogHDL before designing hardware. With the auto-encoder behavior model pre-route simulation, we obtained the cycle accurate results of the parameter of each hidden layer by using MODELSIM. The cycle accurate results are very important factor in designing a parallel-based digital hardware. Finally this paper shows an appropriate operation of behavior model based pre-route simulation. Moreover, we visualized learning latent representations of the first hidden layer with Kyoto natural image dataset.

LIDAR Obstacle Warning and Avoidance System for Unmanned Aircraft

The availability of powerful eye-safe laser sources and the recent advancements in electro-optical and mechanical beam-steering components have allowed laser-based Light Detection and Ranging (LIDAR) to become a promising technology for obstacle warning and avoidance in a variety of manned and unmanned aircraft applications. LIDAR outstanding angular resolution and accuracy characteristics are coupled to its good detection performance in a wide range of incidence angles and weather conditions, providing an ideal obstacle avoidance solution, which is especially attractive in low-level flying platforms such as helicopters and small-to-medium size Unmanned Aircraft (UA). The Laser Obstacle Avoidance Marconi (LOAM) system is one of such systems, which was jointly developed and tested by SELEX-ES and the Italian Air Force Research and Flight Test Centre. The system was originally conceived for military rotorcraft platforms and, in this paper, we briefly review the previous work and discuss in more details some of the key development activities required for integration of LOAM on UA platforms. The main hardware and software design features of this LOAM variant are presented, including a brief description of the system interfaces and sensor characteristics, together with the system performance models and data processing algorithms for obstacle detection, classification and avoidance. In particular, the paper focuses on the algorithm proposed for optimal avoidance trajectory generation in UA applications.