High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform
Real time image and video processing is a demand in
many computer vision applications, e.g. video surveillance, traffic
management and medical imaging. The processing of those video
applications requires high computational power. Thus, the optimal
solution is the collaboration of CPU and hardware accelerators. In
this paper, a Canny edge detection hardware accelerator is proposed.
Edge detection is one of the basic building blocks of video and image
processing applications. It is a common block in the pre-processing
phase of image and video processing pipeline. Our presented
approach targets offloading the Canny edge detection algorithm from
processing system (PS) to programmable logic (PL) taking the
advantage of High Level Synthesis (HLS) tool flow to accelerate the
implementation on Zynq platform. The resulting implementation
enables up to a 100x performance improvement through hardware
acceleration. The CPU utilization drops down and the frame rate
jumps to 60 fps of 1080p full HD input video stream.
[1] Mohammadsadegh Sadri, Christian Weisy, Norbert Wehny, and Luca
Benini: "Energy and Performance Exploration of Accelerator
Coherency Port Using Xilinx ZYNQ", FPGAWorld ’13, September 10-
12, Copenhagen, and Stockholm, ACM
[2] Dobai, R.; Sekanina, L.: "Image filter evolution on the Xilinx Zynq
Platform," Adaptive Hardware and Systems (AHS), 2013 NASA/ESA
Conference on , vol., no., pp.164,171, 24-27 June 2013
[3] Russell, M.; Fischaber, S., "OpenCV based road sign recognition on
Zynq," Industrial Informatics (INDIN), 2013 11th IEEE International
Conference on , vol., no., pp.596,601, 29-31 July 2013
[4] Yan Han; Oruklu, E., "Real-time traffic sign recognition based on Zynq
FPGA and ARM SoCs," Electro/Information Technology (EIT), 2014
IEEE International Conference, pp.373,376, 5-7 June 2014
[5] Josh Monson, Mike Wirthlin, Brad L Hutchings: "Optimization
Techniques for a High Level Synthesis Implementation of the Sobel
Filter"
[6] Hong. Nguyen. T. K, Cecile. Belleudy1 and Tuan. V. Pham2: "Power
Evaluation of Sobel Filter on Xilinx Platform".
[7] Swapnil G. Kavitkar,Prashant L. Paikrao: "FPGA based Image Feature
Extraction Using Xilinx System Generator", (IJCSIT) International
Journal of Computer Science and Information Technologies,2014
[8] Monson, J.; Wirthlin, M.; Hutchings, B.L., "Implementing highperformance,
low-power FPGA-based optical flow accelerators in C,"
Application-Specific Systems, Architectures and Processors (ASAP),
2013 IEEE 24th International Conference, 5-7 June 2013
[9] Christos Gentsos, Calliope-Louisa Sotiropoulou and Spiridon
Nikolaidis:"Real- Time Canny Edge Detection Parallel Implementation
for FPGAs"
[10] Chaithra.N.M., K.V. Ramana Reddy,”Implementation of Canny Edge
Detection Algorithm on FPGA and displaying Image through VGA
Interface”, International Journal of Engineering and Advanced
Technology (IJEAT), ISSN: 2249 8958, Volume-2, Issue-6, August
2013
[11] Fernando Martinez Vallina, Christian Kohn, and Pallav Joshi, ”Zynq All
Programmable SoC Sobel Filter Implementation Using the Vivado HLS
Tool”, XAPP890 (v1.0) September 25, 2012.
[12] Louise H Crockett, Ross A Elliot, Martin A Enderwitz, Robert W
Stewart The Zynq Book: Embedded Processing with the Arm Cortex-
A9 on the Xilinx Zynq-7000 All Programmable Soc Paperback, July 14,
2014
[13] Kester Aernoudt, ”OpenCV, Zynq All Programmable SoC, and Vivado
HLS”,Xilinx,June, 2013
[14] Xilinx,”How to Accelerate OpenCV Applications with the Zynq-7000
All Programmable SoC using Vivado HLS Video Libraries”,August 28,
2013
[15] Xilinx: Zynq Base TRD Wiki http://www.wiki.xilinx.com/Technical
+Articles#TRD
[16] UG925 (v7.0) Zynq-7000 All Programmable SoC ZC702 Base Targeted
Reference Design (Vivado Design Suite 2014.2) User Guide, August
27,2014
[17] Qian Xu, Srenivas Varadarajan, Chaitali Chakrabarti, and Lina J.
Karam,"A Distributed Canny Edge Detector: Algorithm and FPGA
Implementation", IEEE Transactions on Image Processing, Vol. 23, No.
7, July 2014
[18] Bernardo Reis, Paulo Borges, Luis Arthur Vasconcelos, Jo˜ao Marcelo
Teixeira,Veronica Teichrieb, Judith Kelner,” MarkerMatch: an
Embedded Augmented Reality case study”, XII Symposium on Virtual
and Augmented Reality, Natal, RN, Brazil - May 2010
[1] Mohammadsadegh Sadri, Christian Weisy, Norbert Wehny, and Luca
Benini: "Energy and Performance Exploration of Accelerator
Coherency Port Using Xilinx ZYNQ", FPGAWorld ’13, September 10-
12, Copenhagen, and Stockholm, ACM
[2] Dobai, R.; Sekanina, L.: "Image filter evolution on the Xilinx Zynq
Platform," Adaptive Hardware and Systems (AHS), 2013 NASA/ESA
Conference on , vol., no., pp.164,171, 24-27 June 2013
[3] Russell, M.; Fischaber, S., "OpenCV based road sign recognition on
Zynq," Industrial Informatics (INDIN), 2013 11th IEEE International
Conference on , vol., no., pp.596,601, 29-31 July 2013
[4] Yan Han; Oruklu, E., "Real-time traffic sign recognition based on Zynq
FPGA and ARM SoCs," Electro/Information Technology (EIT), 2014
IEEE International Conference, pp.373,376, 5-7 June 2014
[5] Josh Monson, Mike Wirthlin, Brad L Hutchings: "Optimization
Techniques for a High Level Synthesis Implementation of the Sobel
Filter"
[6] Hong. Nguyen. T. K, Cecile. Belleudy1 and Tuan. V. Pham2: "Power
Evaluation of Sobel Filter on Xilinx Platform".
[7] Swapnil G. Kavitkar,Prashant L. Paikrao: "FPGA based Image Feature
Extraction Using Xilinx System Generator", (IJCSIT) International
Journal of Computer Science and Information Technologies,2014
[8] Monson, J.; Wirthlin, M.; Hutchings, B.L., "Implementing highperformance,
low-power FPGA-based optical flow accelerators in C,"
Application-Specific Systems, Architectures and Processors (ASAP),
2013 IEEE 24th International Conference, 5-7 June 2013
[9] Christos Gentsos, Calliope-Louisa Sotiropoulou and Spiridon
Nikolaidis:"Real- Time Canny Edge Detection Parallel Implementation
for FPGAs"
[10] Chaithra.N.M., K.V. Ramana Reddy,”Implementation of Canny Edge
Detection Algorithm on FPGA and displaying Image through VGA
Interface”, International Journal of Engineering and Advanced
Technology (IJEAT), ISSN: 2249 8958, Volume-2, Issue-6, August
2013
[11] Fernando Martinez Vallina, Christian Kohn, and Pallav Joshi, ”Zynq All
Programmable SoC Sobel Filter Implementation Using the Vivado HLS
Tool”, XAPP890 (v1.0) September 25, 2012.
[12] Louise H Crockett, Ross A Elliot, Martin A Enderwitz, Robert W
Stewart The Zynq Book: Embedded Processing with the Arm Cortex-
A9 on the Xilinx Zynq-7000 All Programmable Soc Paperback, July 14,
2014
[13] Kester Aernoudt, ”OpenCV, Zynq All Programmable SoC, and Vivado
HLS”,Xilinx,June, 2013
[14] Xilinx,”How to Accelerate OpenCV Applications with the Zynq-7000
All Programmable SoC using Vivado HLS Video Libraries”,August 28,
2013
[15] Xilinx: Zynq Base TRD Wiki http://www.wiki.xilinx.com/Technical
+Articles#TRD
[16] UG925 (v7.0) Zynq-7000 All Programmable SoC ZC702 Base Targeted
Reference Design (Vivado Design Suite 2014.2) User Guide, August
27,2014
[17] Qian Xu, Srenivas Varadarajan, Chaitali Chakrabarti, and Lina J.
Karam,"A Distributed Canny Edge Detector: Algorithm and FPGA
Implementation", IEEE Transactions on Image Processing, Vol. 23, No.
7, July 2014
[18] Bernardo Reis, Paulo Borges, Luis Arthur Vasconcelos, Jo˜ao Marcelo
Teixeira,Veronica Teichrieb, Judith Kelner,” MarkerMatch: an
Embedded Augmented Reality case study”, XII Symposium on Virtual
and Augmented Reality, Natal, RN, Brazil - May 2010
@article{"International Journal of Information, Control and Computer Sciences:68776", author = "Hanaa M. Abdelgawad and Mona Safar and Ayman M. Wahba", title = "High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform", abstract = "Real time image and video processing is a demand in
many computer vision applications, e.g. video surveillance, traffic
management and medical imaging. The processing of those video
applications requires high computational power. Thus, the optimal
solution is the collaboration of CPU and hardware accelerators. In
this paper, a Canny edge detection hardware accelerator is proposed.
Edge detection is one of the basic building blocks of video and image
processing applications. It is a common block in the pre-processing
phase of image and video processing pipeline. Our presented
approach targets offloading the Canny edge detection algorithm from
processing system (PS) to programmable logic (PL) taking the
advantage of High Level Synthesis (HLS) tool flow to accelerate the
implementation on Zynq platform. The resulting implementation
enables up to a 100x performance improvement through hardware
acceleration. The CPU utilization drops down and the frame rate
jumps to 60 fps of 1080p full HD input video stream.
", keywords = "High Level Synthesis, Canny edge detection, Hardware accelerators, and Computer Vision.", volume = "9", number = "1", pages = "148-5", }
