Abstract: Power quality in terms of power factor, THD and precisely regulated output voltage are the major key factors for efficient operation of power electronic converters. This paper presents an easy and effective active wave shaping control scheme for the pulsed input current drawn by the uncontrolled diode bridge rectifier thereby achieving power factor nearer to unity and also satisfying the THD specifications. It also regulates the output DC-bus voltage. CCM boost power factor correction with constant frequency operation features smaller inductor current ripple resulting in low RMS currents on inductor and switch thus leading to low electromagnetic interference. The objective of this work is to develop an active PFC control circuit using CCM boost converter implementing variable duty cycle control. The proposed scheme eliminates inductor current sensing requirements yet offering good performance and satisfactory results for maintaining the power quality. Simulation results have been presented which covers load changes also.
Abstract: Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.
Abstract: This paper presents a generalized d-q model of n- phase induction motor drive. Multi -phase (n-phase) induction motor (more than three phases) drives possess several advantages over conventional three-phase drives, such as reduced current/phase without increasing voltage/phase, lower torque pulsation, higher torque density, fault tolerance, stability, high efficiency and lower current ripple. When the number of phases increases, it is also possible to increase the power in the same frame. In this paper, a generalized dq-axis model is developed in Matlab/Simulink for an n-phase induction motor. The simulation results are presented for 5, 6, 7, 9 and 12 phase induction motor under varying load conditions. Transient response of the multi-phase induction motors are given for different number of phases. Fault tolerant feature is also analyzed for 5-phase induction motor drive.
Abstract: In this paper the principle, basic torque theory and design optimisation of a six-phase reluctance dc machine are considered. A trapezoidal phase current waveform for the machine drive is proposed and evaluated to minimise ripple torque. Low cost normal laminated salient-pole rotors with and without slits and chamfered poles are investigated. The six-phase machine is optimised in multi-dimensions by linking the finite-element analysis method directly with an optimisation algorithm; the objective function is to maximise the torque per copper losses of the machine. The armature reaction effect is investigated in detail and found to be severe. The measured and calculated torque performances of a 35 kW optimum designed six-phase reluctance dc machine drive are presented.
Abstract: Exchange algorithm with constraints on magnitude and phase error separately in new way is presented in this paper. An important feature of the algorithms presented in this paper is that they allow for design constraints which often arise in practical filter design problems. Meeting required minimum stopband attenuation or a maximum deviation from the desired magnitude and phase responses in the passbands are common design constraints that can be handled by the methods proposed here. This new algorithm may have important advantages over existing technique, with respect to the speed and stability of convergence, memory requirement and low ripples.
Abstract: In this paper, an optimal design of linear phase digital
high pass finite impulse response (FIR) filter using Particle Swarm
Optimization with Constriction Factor and Inertia Weight Approach
(PSO-CFIWA) has been presented. In the design process, the filter
length, pass band and stop band frequencies, feasible pass band and
stop band ripple sizes are specified. FIR filter design is a multi-modal
optimization problem. The conventional gradient based optimization
techniques are not efficient for digital filter design. Given the filter
specifications to be realized, the PSO-CFIWA algorithm generates a
set of optimal filter coefficients and tries to meet the ideal frequency
response characteristic. In this paper, for the given problem, the
designs of the optimal FIR high pass filters of different orders have
been performed. The simulation results have been compared to those
obtained by the well accepted algorithms such as Parks and
McClellan algorithm (PM), genetic algorithm (GA). The results
justify that the proposed optimal filter design approach using PSOCFIWA
outperforms PM and GA, not only in the accuracy of the
designed filter but also in the convergence speed and solution
quality.
Abstract: A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.
Abstract: Efficient modulo 2n+1 adders are important for
several applications including residue number system, digital signal
processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented
number system. The proposed approach is introduced for the
reduction of the power dissipated. In a conventional modulo 2n+1
adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit
circuits, the diminished-1 and carry save diminished-1 number
systems can be effectively used in applications. In the paper, we also
derive two new architectures for designing modulo 2n+1 adder, based
on n-bit ripple-carry adder. The first architecture is a faster design
whereas the second one uses less hardware. In the proposed method,
the special treatment required for zero operands in Diminished-1
number system is removed. In the fastest modulo 2n+1 adders in
normal binary system, there are 3-operand adders. This problem is
also resolved in this paper. The proposed architectures are compared
with some efficient adders based on ripple-carry adder and highspeed
adder. It is shown that the hardware overhead and power
consumption will be reduced. As well as power reduction, in some
cases, power-delay product will be also reduced.
Abstract: This paper proposes a low-voltage and low-power
fully integrated digitally tuned continuous-time channel selection
filter for WiMAX applications. A 5th-order elliptic low-pass filter is
realized in a Gm-C topology. The bandwidth of the fully differential
filter is reconfigurable from 2.5MHz to 20MHz (8x) for different
requirements in WiMAX applications. The filter is simulated in a
standard 90nm CMOS process. Simulation results show the THD
(@Vout =100mVpp) is less than -66dB. The in-band ripple of the
filter is about 0.15dB. The filter consumes 1.5mW from a supply
voltage of 0.9V.
Abstract: In this paper, we analyze the rotor eddy currents losses provoqued by the stator slot harmonics developed in the permanent magnets or pole pieces of synchronous machines. An analytical approach is presented to evaluate the effect of slot ripples on rotor field and losses calculation. This analysis is then tested on a model by 2D/3D finite element (FE) calculation. The results show a good agreement on loss calculations when skin effect is negligible and the magnet is considered.
Abstract: This paper presented a theoretical and numerical investigation of the Compact Antenna Test Range (CATR) equipped with Super Hybrid Modulated Segmented Exponential Serrations (SHMSES). The investigation was based on diffraction theory and, more specifically, the Fresnel diffraction formulation. The CATR provides uniform illumination within the Fresnel region to test antenna. Application of serrated edges has been shown to be a good method to control diffraction at the edges of the reflectors. However, in order to get some insight into the positive effect of serrated edges a less rigorous analysis technique known as Physical Optics (PO) may be used. Ripple free and enhanced quiet zone width are observed for specific values of width and height modulation factors per serrations. The performance of SHMSE serrated reflector is evaluated in order to observe the effects of edge diffraction on the test zone fields.
Abstract: Variable digital filters are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied. In this paper, we propose a design method of variable FIR digital filters with an approximate linear phase characteristic in the passband. The proposed variable FIR filters have some large attenuation in stopband and their large attenuation can be varied by spectrum parameters. In the proposed design method, a quasi-equiripple characteristic can be obtained by using an iterative weighted least square method. The usefulness of the proposed design method is verified through some examples.
Abstract: A DC-to-DC converter for applications involving a
source with widely varying voltage conditions with loads requiring
constant voltage from full load down to no load is presented.
The switching regulator considered is a Buck converter with Pulse
Skipping Modulation control whereby pulses applied to the switch
are blocked or released on output voltage crossing a predetermined
value. Results of the study on the performance of regulator circuit
are presented. The regulator regulates over a wide input voltage range
with slightly higher ripple content and good transient response. Input
current spectrum indicates a good EMI performance with crowding
of components at low frequency range.
Abstract: A new estimator for evolutionary spectrum (ES) based
on short time Fourier transform (STFT) and modified group delay
function (MGDF) by signal decomposition (SD) is proposed. The
STFT due to its built-in averaging, suppresses the cross terms and the
MGDF preserves the frequency resolution of the rectangular window
with the reduction in the Gibbs ripple. The present work overcomes
the magnitude distortion observed in multi-component non-stationary
signals with STFT and MGDF estimation of ES using SD. The SD is
achieved either through discrete cosine transform based harmonic
wavelet transform (DCTHWT) or perfect reconstruction filter banks
(PRFB). The MGDF also improves the signal to noise ratio by
removing associated noise. The performance of the present method is
illustrated for cross chirp and frequency shift keying (FSK) signals,
which indicates that its performance is better than STFT-MGDF
(STFT-GD) alone. Further its noise immunity is better than STFT.
The SD based methods, however cannot bring out the frequency
transition path from band to band clearly, as there will be gap in the
contour plot at the transition. The PRFB based STFT-SD shows good
performance than DCTHWT decomposition method for STFT-GD.
Abstract: This paper presents a pulse doubling technique in a 12-pulse ac-dc converter which supplies direct torque controlled motor drives (DTCIMD-s) in order to have better power quality conditions at the point of common coupling. The proposed technique increases the number of rectification pulses without significant changes in the installations and yields in harmonic reduction in both ac and dc sides. The 12-pulse rectified output voltage is accomplished via two paralleled six-pulse ac-dc converters each of them consisting of three-phase diode bridge rectifier. An autotransformer is designed to supply the rectifiers. The design procedure of magnetics is in a way such that makes it suitable for retrofit applications where a six-pulse diode bridge rectifier is being utilized. Independent operation of paralleled diode-bridge rectifiers, i.e. dc-ripple re-injection methodology, requires a Zero Sequence Blocking Transformer (ZSBT). Finally, a tapped interphase reactor is connected at the output of ZSBT to double the pulse numbers of output voltage up to 24 pulses. The aforementioned structure improves power quality criteria at ac mains and makes them consistent with the IEEE-519 standard requirements for varying loads. Furthermore, near unity power factor is obtained for a wide range of DTCIMD operation. A comparison is made between 6- pulse, 12-pulse, and proposed converters from view point of power quality indices. Results show that input current total harmonic distortion (THD) is less than 5% for the proposed topology at various loads.
Abstract: This paper presents a speed sensorless direct torque
control scheme using space vector modulation (DTC-SVM) for
permanent magnet synchronous motor (PMSM) drive based a Model
Reference Adaptive System (MRAS) algorithm and stator resistance
estimator. The MRAS is utilized to estimate speed and stator
resistance and compensate the effects of parameter variation on stator
resistance, which makes flux and torque estimation more accurate
and insensitive to parameter variation. In other hand the use of SVM
method reduces the torque ripple while achieving a good dynamic
response. Simulation results are presented and show the effectiveness
of the proposed method.
Abstract: Direct Torque Control is a control technique in AC
drive systems to obtain high performance torque control. The
conventional DTC drive contains a pair of hysteresis comparators.
DTC drives utilizing hysteresis comparators suffer from high torque
ripple and variable switching frequency. The most common solution
to those problems is to use the space vector depends on the reference
torque and flux. In this Paper The space vector modulation technique
(SVPWM) is applied to 2 level inverter control in the proposed
DTC-based induction motor drive system, thereby dramatically
reducing the torque ripple. Then the controller based on space vector
modulation is designed to be applied in the control of Induction
Motor (IM) with a three-level Inverter. This type of Inverter has
several advantages over the standard two-level VSI, such as a greater
number of levels in the output voltage waveforms, Lower dV/dt, less
harmonic distortion in voltage and current waveforms and lower
switching frequencies. This paper proposes a general SVPWM
algorithm for three-level based on standard two-level SVPWM. The
proposed scheme is described clearly and simulation results are
reported to demonstrate its effectiveness. The entire control scheme is
implemented with Matlab/Simulink.
Abstract: In this paper by using the port-controlled Hamiltonian
(PCH) systems theory, a full-order nonlinear controlled model is first
developed. Then a nonlinear passivity-based robust adaptive control
(PBRAC) of switched reluctance motor in the presence of external
disturbances for the purpose of torque ripple reduction and
characteristic improvement is presented. The proposed controller
design is separated into the inner loop and the outer loop controller.
In the inner loop, passivity-based control is employed by using
energy shaping techniques to produce the proper switching function.
The outer loop control is employed by robust adaptive controller to
determine the appropriate Torque command. It can also overcome the
inherent nonlinear characteristics of the system and make the whole
system robust to uncertainties and bounded disturbances. A 4KW 8/6
SRM with experimental characteristics that takes magnetic saturation
into account is modeled, simulation results show that the proposed
scheme has good performance and practical application prospects.
Abstract: Recent developments in Soft computing techniques,
power electronic switches and low-cost computational hardware have
made it possible to design and implement sophisticated control
strategies for sensorless speed control of AC motor drives. Such an
attempt has been made in this work, for Sensorless Speed Control of
Induction Motor (IM) by means of Direct Torque Fuzzy Control
(DTFC), PI-type fuzzy speed regulator and MRAS speed estimator
strategy, which is absolutely nonlinear in its nature. Direct torque
control is known to produce quick and robust response in AC drive
system. However, during steady state, torque, flux and current ripple
occurs. So, the performance of conventional DTC with PI speed
regulator can be improved by implementing fuzzy logic techniques.
Certain important issues in design including the space vector
modulated (SVM) 3-Ф voltage source inverter, DTFC design,
generation of reference torque using PI-type fuzzy speed regulator
and sensor less speed estimator have been resolved. The proposed
scheme is validated through extensive numerical simulations on
MATLAB. The simulated results indicate the sensor less speed
control of IM with DTFC and PI-type fuzzy speed regulator provides
satisfactory high dynamic and static performance compare to
conventional DTC with PI speed regulator.
Abstract: It is observed that the Weighted least-square (WLS)
technique, including the modifications, results in equiripple error
curve. The resultant error as a percent of the ideal value is highly
non-uniformly distributed over the range of frequencies for which the
differentiator is designed. The present paper proposes a modification
to the technique so that the optimization procedure results in lower
maximum relative error compared to the ideal values. Simulation
results for first order as well as higher order differentiators are given
to illustrate the excellent performance of the proposed method.