A New Approach to Design an Efficient CIC Decimator Using Signed Digit Arithmetic
Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.
[1] L. R. Rabiner and B. Gold, Theory and Application of Digital Signal
Processing. Englewood Cliffs, New Jersey: Prentice Hall, 1975.
[2] E. B. Hogenauer, "An Economical Class of Digital Filters for
Decimation and Interpolation", IEEE Transactions on Acoustics, Speech,
and Signal Processing, Vol. ASSP-29, pp. 155-162, April 1981.
[3] Jovanovic Dolecek and Fred Harris, “Design of CIC Compensator Filter
in a Digital IF Receiver”, IEEE Trans. on Circuits and Systems 2008.
[4] Y. Djadi, T. A. Kwasniewski, C. Chan and V. Szwarc, "A High
Throughput Programmable Decimation and Interpolation Filter",
Proceeding of the international Conference on Signal Processing
Applications and Technology, pp. 1743- 1748, 1994
[5] Yonghong Gao, Lihong Jia and Tenhunen, H. “A partial-polyphase
VLSI architecture for very high speed CIC decimation filters”, Twelfth
Annual IEEE International ASIC/SOC Conference, Stockholm, pp. 391-
395, 1999
[6] A. Kwentus, O. Lee, and A. N. Willson, Jr., "A 250 M sample/sec
Programmable Cascaded Integrator-Comb Decimation Filter",
Proceeding VISI Signal Processing, IX, pp. 231-240, 1996.
[7] Jovanovic-Dolecek and G., Mitra, S. K. , “ CIC filter for rational sample rate
conversion”, Proc. of IEEE Asia Pacific Conference on Circuits and
Systems – APCCAS, pp. 918-921, 2006
[8] G. J. Dolecek and Fred Harris, “Design of wideband CIC compensator
filter for a digital IF receiver”, Digital Signal Processing 19, ELSEVIER,
pp. 827–837, April, 2009
[9] Gordana Jovanovic Dolecek and Fred Harris, “On Design of Two- Stage
CIC Compensation Filter”, IEEE International Symposium on Industrial
Electronics, Seoul, Korea , pp. 903-908, July 5-8, 2009
[10] G. J. Dolecek and M. Laddomada, “An Economical Class of Droop-
Compensated Generalized Comb Filters: Analysis and Design”, IEEE
Transactions on Circuits and Systems-II, Vol. 57, No.4, pp. 275-279,
April 2010.
[11] Alfonso Fernandez-Vazquez and Gordana Jovanovic Dolecek,
“Passband and Stopband CIC Improvement Based on Efficient IIR Filter
Structure”, IEEE Transactions on Circuits and Systems, 2010.
[12] V. G. Oklobdzija and E. R. Barnes, "On Implementing Addition In VLSI
Technology," IEEE Journal of Parallel and Distributed Computing, No.
5, pp. 716-728, 1988.
[13] Kogge, P.M. and Stone, H.S., “A Parallel Algorithms for the Efficient
Solution of a General Class of Recurrence Equations”, IEEE
Transactions on Computers, Vol. C-22, No 8, Aug.1973. pp. 786-793.
[14] Ling H., "High Speed Binary Parallel Adder", IEEE Transactions on
Electronic Computers, EC-15, pp.799-809, October, 1966.
[15] J. E. Robertson, “A Deterministic Procedure for the Design of Carry-
Save Adders and Borrow-Save Subtractors,” University of Illinois,
Urbana-Champaign, Dept. of Computer Science, Report No. 235, July
1967.
[16] A. Avizienis, "Signed-digit number representation for fast parallel
arithmetics", IRE Transactions on Electronic Computers, pp. 389, 1961.
[17] N. Takagi, H. Yasuura and S. Yajima, “High Speed VLSI Multiplication
Algorithm with a Redundant Binary Addition Tree,” IEEE Trans. Comp.
vol. 34 pp. 789-796, Sept. 1985.
[18] O. J. Bedrij, "Carry-Select Adder", IRE Transactions on Electronic
Computers, pp. 340, June 1962.
[19] H. J. Oh and Y. H. Lee, “Multiplierless FIR Filters Based on Cyclotomic
and interpolated Second-order Polynomial with Powers-of-two
Coefficients” Procedding Midwest Symp. Circuits System, Sacramento,
CA, Aug. 1997.
[20] Jovanović-Doleček, G. and Mitra, S. K., “A new two-stage sharpened
comb decimator”, IEEE Transactions on Circuits and Systems – I:
Regular Papers, 52(7), pp. 1414-1420, 2005.
[21] H. Aboushady, Y. Dumonteix, M. M. Loerat, and H. Mehrezz, “Efficient
polyphase decomposition of comb decimation filters in Σ-] analog-todigital
converters,” IEEE Transactions on Circuits & Systems – II:
Analog and Digital Signal Processing, vol. 48, pp. 898-903, October
2001.
[22] H. K. Yang and W. M. Snelgrove, “High Speed Polyphase CIC
Decimation Filters", Proceeding of 1996 IEEE International Conference
On Communications, pp. II.229- II.233, Atlanta, US, May 1996.
[23] Saramäki T. and Ritoniemi, T., “A modified comb filter structure for
decimation”, Proc. IEEE International Symp. Circuits and Systems –
ISCAS, pp. 2353-2356, 1997.
[24] Abu-Al-Saud and Stuber, “Efficient sample rate conversion for software
radio systems”, IEEE Transactions on Signal Processing, Volume 54(3),
pp. 932 – 939, 2006.
[25] Lo Presti L., “Efficient modified-sinc filters for sigma-delta A/D
converters,” IEEE Transactions on Circuits & Systems – II: Analog and
Digital Signal Processing, vol. 47, pp. 1204-1213, November 2000.
[26] Kaiser, J. F. and Hamming, R. W., “Sharpening the response of a
symmetric nonrecursive filter. IEEE Trans. Acoustics, Speech, and
Signal Processing, 25(5)”, pp. 415-422, 1977
[27] G. Jovanovic-Dolecek and S. K. Mitra, “Sharpened comb decimator
with improved magnitude response,” Proc. 2004 International
Conference on Acoustics, Speech, and Signal Processing, Canada, vol.2,
pp. 393-396, May 2004.
[28] A. J. Kwentus, Z. Jiang, and A. N. Willson, Jr., “Application of filter
sharpening to cascaded integrator-comb decimation filters,” IEEE
Transactions on Signal Processing, vol.45, pp.457-467, February 1997.
[29] Laddomada, M. and Mondin, M., “Decimation schemes for ΣΔ k/
Cconverters based on Kaiser and Hamming sharpened filters”, IEE
Proceedings - Vision, Image and Signal Processing, 151(4), pp. 287-296,
2004.
[30] Laddomada M., “Generalized Comb Decimation Filters for ΣΔ k/C
Converters: Analysis and Design”, IEEE Transactions on Circuits and
Systems I: Regular Papers, 54, pp. 994-1005, 2007.
[31] Phatak D. S. and I. Koren, “Hybrid Signed-Digit Number Systems: A
Unified Framework for Redundant Number Representations with
Bounded Carry Propagation Chains” IEEE Trans. on Computers, Vol.
43, No. 8, pp 880-891, Aug. 1994.
[32] Kei-Yong Khoo , Zhan Yu and Wilson, A.N., “Efficient high-speed CIC
decimation filter”, Eleventh Annual IEEE International ASIC
Conference, California, pp. 251-254, 13-16 Sep 1998
[33] Dolecek, G.J. and Carmona, J.D. “Generalized CIC-cosine decimation
filter”, IEEE Symposium on Industrial Electronics & Applications
(ISIEA), Mexico, pp. 640-645, 3-5 Oct. 2010.
[34] Pecotic, M.G., Molnar, G. and Vucic, M. “Design of CIC compensators
with SPT coefficients based on interval analysis”, Proceedings of the
35th International Convention MIPRO, Croatia, pp. 123-128, 21-25 May
2012.
[1] L. R. Rabiner and B. Gold, Theory and Application of Digital Signal
Processing. Englewood Cliffs, New Jersey: Prentice Hall, 1975.
[2] E. B. Hogenauer, "An Economical Class of Digital Filters for
Decimation and Interpolation", IEEE Transactions on Acoustics, Speech,
and Signal Processing, Vol. ASSP-29, pp. 155-162, April 1981.
[3] Jovanovic Dolecek and Fred Harris, “Design of CIC Compensator Filter
in a Digital IF Receiver”, IEEE Trans. on Circuits and Systems 2008.
[4] Y. Djadi, T. A. Kwasniewski, C. Chan and V. Szwarc, "A High
Throughput Programmable Decimation and Interpolation Filter",
Proceeding of the international Conference on Signal Processing
Applications and Technology, pp. 1743- 1748, 1994
[5] Yonghong Gao, Lihong Jia and Tenhunen, H. “A partial-polyphase
VLSI architecture for very high speed CIC decimation filters”, Twelfth
Annual IEEE International ASIC/SOC Conference, Stockholm, pp. 391-
395, 1999
[6] A. Kwentus, O. Lee, and A. N. Willson, Jr., "A 250 M sample/sec
Programmable Cascaded Integrator-Comb Decimation Filter",
Proceeding VISI Signal Processing, IX, pp. 231-240, 1996.
[7] Jovanovic-Dolecek and G., Mitra, S. K. , “ CIC filter for rational sample rate
conversion”, Proc. of IEEE Asia Pacific Conference on Circuits and
Systems – APCCAS, pp. 918-921, 2006
[8] G. J. Dolecek and Fred Harris, “Design of wideband CIC compensator
filter for a digital IF receiver”, Digital Signal Processing 19, ELSEVIER,
pp. 827–837, April, 2009
[9] Gordana Jovanovic Dolecek and Fred Harris, “On Design of Two- Stage
CIC Compensation Filter”, IEEE International Symposium on Industrial
Electronics, Seoul, Korea , pp. 903-908, July 5-8, 2009
[10] G. J. Dolecek and M. Laddomada, “An Economical Class of Droop-
Compensated Generalized Comb Filters: Analysis and Design”, IEEE
Transactions on Circuits and Systems-II, Vol. 57, No.4, pp. 275-279,
April 2010.
[11] Alfonso Fernandez-Vazquez and Gordana Jovanovic Dolecek,
“Passband and Stopband CIC Improvement Based on Efficient IIR Filter
Structure”, IEEE Transactions on Circuits and Systems, 2010.
[12] V. G. Oklobdzija and E. R. Barnes, "On Implementing Addition In VLSI
Technology," IEEE Journal of Parallel and Distributed Computing, No.
5, pp. 716-728, 1988.
[13] Kogge, P.M. and Stone, H.S., “A Parallel Algorithms for the Efficient
Solution of a General Class of Recurrence Equations”, IEEE
Transactions on Computers, Vol. C-22, No 8, Aug.1973. pp. 786-793.
[14] Ling H., "High Speed Binary Parallel Adder", IEEE Transactions on
Electronic Computers, EC-15, pp.799-809, October, 1966.
[15] J. E. Robertson, “A Deterministic Procedure for the Design of Carry-
Save Adders and Borrow-Save Subtractors,” University of Illinois,
Urbana-Champaign, Dept. of Computer Science, Report No. 235, July
1967.
[16] A. Avizienis, "Signed-digit number representation for fast parallel
arithmetics", IRE Transactions on Electronic Computers, pp. 389, 1961.
[17] N. Takagi, H. Yasuura and S. Yajima, “High Speed VLSI Multiplication
Algorithm with a Redundant Binary Addition Tree,” IEEE Trans. Comp.
vol. 34 pp. 789-796, Sept. 1985.
[18] O. J. Bedrij, "Carry-Select Adder", IRE Transactions on Electronic
Computers, pp. 340, June 1962.
[19] H. J. Oh and Y. H. Lee, “Multiplierless FIR Filters Based on Cyclotomic
and interpolated Second-order Polynomial with Powers-of-two
Coefficients” Procedding Midwest Symp. Circuits System, Sacramento,
CA, Aug. 1997.
[20] Jovanović-Doleček, G. and Mitra, S. K., “A new two-stage sharpened
comb decimator”, IEEE Transactions on Circuits and Systems – I:
Regular Papers, 52(7), pp. 1414-1420, 2005.
[21] H. Aboushady, Y. Dumonteix, M. M. Loerat, and H. Mehrezz, “Efficient
polyphase decomposition of comb decimation filters in Σ-] analog-todigital
converters,” IEEE Transactions on Circuits & Systems – II:
Analog and Digital Signal Processing, vol. 48, pp. 898-903, October
2001.
[22] H. K. Yang and W. M. Snelgrove, “High Speed Polyphase CIC
Decimation Filters", Proceeding of 1996 IEEE International Conference
On Communications, pp. II.229- II.233, Atlanta, US, May 1996.
[23] Saramäki T. and Ritoniemi, T., “A modified comb filter structure for
decimation”, Proc. IEEE International Symp. Circuits and Systems –
ISCAS, pp. 2353-2356, 1997.
[24] Abu-Al-Saud and Stuber, “Efficient sample rate conversion for software
radio systems”, IEEE Transactions on Signal Processing, Volume 54(3),
pp. 932 – 939, 2006.
[25] Lo Presti L., “Efficient modified-sinc filters for sigma-delta A/D
converters,” IEEE Transactions on Circuits & Systems – II: Analog and
Digital Signal Processing, vol. 47, pp. 1204-1213, November 2000.
[26] Kaiser, J. F. and Hamming, R. W., “Sharpening the response of a
symmetric nonrecursive filter. IEEE Trans. Acoustics, Speech, and
Signal Processing, 25(5)”, pp. 415-422, 1977
[27] G. Jovanovic-Dolecek and S. K. Mitra, “Sharpened comb decimator
with improved magnitude response,” Proc. 2004 International
Conference on Acoustics, Speech, and Signal Processing, Canada, vol.2,
pp. 393-396, May 2004.
[28] A. J. Kwentus, Z. Jiang, and A. N. Willson, Jr., “Application of filter
sharpening to cascaded integrator-comb decimation filters,” IEEE
Transactions on Signal Processing, vol.45, pp.457-467, February 1997.
[29] Laddomada, M. and Mondin, M., “Decimation schemes for ΣΔ k/
Cconverters based on Kaiser and Hamming sharpened filters”, IEE
Proceedings - Vision, Image and Signal Processing, 151(4), pp. 287-296,
2004.
[30] Laddomada M., “Generalized Comb Decimation Filters for ΣΔ k/C
Converters: Analysis and Design”, IEEE Transactions on Circuits and
Systems I: Regular Papers, 54, pp. 994-1005, 2007.
[31] Phatak D. S. and I. Koren, “Hybrid Signed-Digit Number Systems: A
Unified Framework for Redundant Number Representations with
Bounded Carry Propagation Chains” IEEE Trans. on Computers, Vol.
43, No. 8, pp 880-891, Aug. 1994.
[32] Kei-Yong Khoo , Zhan Yu and Wilson, A.N., “Efficient high-speed CIC
decimation filter”, Eleventh Annual IEEE International ASIC
Conference, California, pp. 251-254, 13-16 Sep 1998
[33] Dolecek, G.J. and Carmona, J.D. “Generalized CIC-cosine decimation
filter”, IEEE Symposium on Industrial Electronics & Applications
(ISIEA), Mexico, pp. 640-645, 3-5 Oct. 2010.
[34] Pecotic, M.G., Molnar, G. and Vucic, M. “Design of CIC compensators
with SPT coefficients based on interval analysis”, Proceedings of the
35th International Convention MIPRO, Croatia, pp. 123-128, 21-25 May
2012.
@article{"International Journal of Electrical, Electronic and Communication Sciences:66261", author = "Vishal Awasthi and Krishna Raj", title = "A New Approach to Design an Efficient CIC Decimator Using Signed Digit Arithmetic", abstract = "Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.
", keywords = "Sampling rate conversion, Multirate Filtering, Compensation Theory, Decimation filter, CIC filter, Redundant signed digit arithmetic, Fast adders.", volume = "7", number = "11", pages = "1483-10", }
