Abstract: The operation of grid-connected inverters necessity a
single-phase phase locked loop (PLL) is proposed in this article to
accurately and quickly estimate and detect the grid phase angle. This
article presents the improvement of a method of phase-locked loop.
The novelty is to generate a method (PLL) of synchronizing the grid
with a Notch filter based on adaptive fuzzy logic for inverter systems
connected to the grid. The performance of the proposed method was
tested under normal and abnormal operating conditions (amplitude,
frequency and phase shift variations). In addition, simulation results
with ISPM software are developed to verify the effectiveness of the
proposed method strategy. Finally, the experimental test will be used
to extract the result and discuss the validity of the proposed algorithm.
Abstract: In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.
Abstract: This paper presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.
Abstract: In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.
Abstract: The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.
Abstract: This paper presents a model predictive control (MPC)
of a utility interactive (UI) single phase inverter (SPI) for a
photovoltaic (PV) system at residential/distribution level. The
proposed model uses single-phase phase locked loop (PLL) to
synchronize SPI with the grid and performs MPC control in a dq
reference frame. SPI model consists of boost converter (BC),
maximum power point tracking (MPPT) control, and a full bridge
(FB) voltage source inverter (VSI). No PI regulators to tune and
carrier and modulating waves are required to produce switching
sequence. Instead, the operational model of VSI is used to synthesize
sinusoidal current and track the reference. Model is validated using a
three kW PV system at the input of UI-SPI in Matlab/Simulink.
Implementation and results demonstrate simplicity and accuracy, as
well as reliability of the model.
Abstract: This paper presents a simulation and mathematical model of stand-alone solar-wind-diesel based hybrid energy system (HES). A power management system is designed for multiple energy resources in a stand-alone hybrid energy system. Both Solar photovoltaic and wind energy conversion system consists of maximum power point tracking (MPPT), voltage regulation, and basic power electronic interfaces. An additional diesel generator is included to support and improve the reliability of stand-alone system when renewable energy sources are not available. A power management strategy is introduced to distribute the generated power among resistive load banks. The frequency regulation is developed with conventional phase locked loop (PLL) system. The power management algorithm was applied in Matlab®/Simulink® to simulate the results.
Abstract: This paper presents a method for obtaining the
desired reference current for Voltage Source Converter (VSC) of the Shunt Active Power Filter (SAPF) using Synchronous Reference Frame Theory. The method relies on the performance of the Proportional-Integral (PI) controller for
obtaining the best control performance of the SAPF. To
improve the performance of the PI controller, the feedback
path to the integral term is introduced to compensate the
winding up phenomenon due to integrator. Using Reference
Frame Transformation, reference signals are transformed from
a - b - c stationery frame to 0 - d - q rotating frame.
Using the PI controller, the reference signals in the 0 - d - q rotating frame are controlled to get the desired reference signals for the Pulse Width Modulation. The synchronizer, the Phase Locked Loop (PLL) with PI filter is used for
synchronization, with much emphasis on minimizing delays. The system performance is examined with Shunt Active Power Filter simulation model.
Abstract: Phase locked loops in 10 Gb/s and faster data links are
low phase noise devices. Characterization of their phase jitter
transfer functions is difficult because the intrinsic noise of the PLLs
is comparable to the phase noise of the reference clock signal. The
problem is solved by using a linear model to account for the intrinsic
noise. This study also introduces a novel technique for measuring the
transfer function. It involves the use of the reference clock as a
source of wideband excitation, in contrast to the commonly used
sinusoidal excitations at discrete frequencies. The data reported here
include the intrinsic noise of a PLL for 10 Gb/s links and the jitter
transfer function of a PLL for 12.8 Gb/s links. The measured transfer
function suggests that the PLL responded like a second order linear
system to a low noise reference clock.
Abstract: This paper describes the design of a programmable
FSK-modulator based on VCO and its implementation in 0.35m
CMOS process. The circuit is used to transmit digital data at
100Kbps rate in the frequency range of 400-600MHz. The design
and operation of the modulator is discussed briefly. Further the
characteristics of PLL, frequency synthesizer, VCO and the whole
design are elaborated. The variation among the proposed and tested
specifications is presented. Finally, the layout of sub-modules, pin
configurations, final chip and test results are presented.
Abstract: Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.
Abstract: In this paper the reference current for Voltage Source
Converter (VSC) of the Shunt Active Power Filter (SAPF) is
generated using Synchronous Reference Frame method,
incorporating the PI controller with anti-windup scheme. The
proposed method improves the harmonic filtering by compensating
the winding up phenomenon caused by the integral term of the PI
controller.
Using Reference Frame Transformation, the current is transformed
from om a - b - c stationery frame to rotating 0 - d - q frame. Using
the PI controller, the current in the 0 - d - q frame is controlled to
get the desired reference signal. A controller with integral action
combined with an actuator that becomes saturated can give some
undesirable effects. If the control error is so large that the integrator
saturates the actuator, the feedback path becomes ineffective because
the actuator will remain saturated even if the process output changes.
The integrator being an unstable system may then integrate to a very
large value, the phenomenon known as integrator windup.
Implementing the integrator anti-windup circuit turns off the
integrator action when the actuator saturates, hence improving the
performance of the SAPF and dynamically compensating harmonics
in the power network. In this paper the system performance is
examined with Shunt Active Power Filter simulation model.
Abstract: Phase locked loops for data links operating at 10 Gb/s
or faster are low phase noise devices designed to operate with a low
jitter reference clock. Characterization of their jitter transfer function
is difficult because the intrinsic noise of the device is comparable to
the random noise level in the reference clock signal. A linear model
is proposed to account for the intrinsic noise of a PLL. The intrinsic
noise data of a PLL for 10 Gb/s links is presented. The jitter transfer
function of a PLL in a test chip for 12.8 Gb/s data links was
determined in experiments using the 400 MHz reference clock as the
source of simultaneous excitations over a wide range of frequency.
The result shows that the PLL jitter transfer function can be
approximated by a second order linear model.
Abstract: The designing of charge pump with high gain Op-
Amp is a challenging task for getting faithful response .Design of
high performance phase locked loop require ,a design of high
performance charge pump .We have designed a operational amplifier
for reducing the error caused by high speed glitch in a transistor and
mismatch currents . A separate Op-Amp has designed in 180 nm
CMOS technology by CADENCE VIRTUOSO tool. This paper
describes the design of high performance charge pump for GHz
CMOS PLL targeting orthogonal frequency division multiplexing
(OFDM) application. A high speed low power consumption Op-Amp
with more than 500 MHz bandwidth has designed for increasing the
speed of charge pump in Phase locked loop.
Abstract: This article deals to describe the simulation
investigation of the digital phase locked loop implemented in
software (SDPLL). SDPLL has been developed for speed drives of an
induction motor in scalar strategy. A drive was implemented and
simulation results are presented to verify the robustness against motor
parameter variation and regulation speed.
Abstract: An efficient architecture for low jitter All Digital
Phase Locked Loop (ADPLL) suitable for high speed SoC
applications is presented in this paper. The ADPLL is designed using
standard cells and described by Hardware Description Language
(HDL). The ADPLL implemented in a 90 nm CMOS process can
operate from 10 to 200 MHz and achieve worst case frequency
acquisition in 14 reference clock cycles. The simulation result shows
that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps
at 100MHz. Since the digitally controlled oscillator (DCO) can
achieve both high resolution and wide frequency range, it can meet
the demands of system-level integration. The proposed ADPLL can
easily be ported to different processes in a short time. Thus, it can
reduce the design time and design complexity of the ADPLL, making
it very suitable for System-on-Chip (SoC) applications.