Abstract: The modular multilevel converter (MMC) is one of the advanced topologies for medium and high-voltage applications. In high-power, high-voltage MMC, a large number of switching power devices are required. These switching power devices (IGBT) considerable switching losses. This paper analyzes the performance of different discontinuous pulse width modulation (DPWM) techniques and compares the results against a conventional carrier based pulse width modulation method, in order to reduce the switching losses of an MMC. The DPWM reference wave can be generated by adding the zero-sequence component to the original (sine) reference modulation signal. The result of the addition gives the reference signal of DPWM techniques. To minimize the switching losses of the MMC, the clamping period is controlled according to the absolute value of the output load current. No switching is generated in the clamping period so overall switching of the power device is reduced. The simulation result of the different DPWM techniques is compared with conventional carrier-based pulse-width modulation technique.
Abstract: The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.
Abstract: This paper describes design of a digital feedback loop
for a low switching frequency dc-dc switching converters. Low
switching frequencies were selected in this design. A look up table
for the digital PID (proportional integrator differentiator)
compensator was implemented using Altera Stratix II with built-in
ADC (analog-to-digital converter) to achieve this hardware
realization. Design guidelines are given for the PID compensator,
high frequency DPWM (digital pulse width modulator) and moving
average filter.
Abstract: A new power regulator controller with multiple-access
PID compensator is proposed, which can achieve a minimum memory
requirement for fully table look-up. The proposed regulator controller
employs hysteresis comparators, an error process unit (EPU) for
voltage regulation, a multiple-access PID compensator and a lowpower-
consumption digital PWM (DPWM). Based on the multipleaccess
mechanism, the proposed controller can alleviate the penalty of
large amount of memory employed for fully table look-up based PID
compensator in the applications of power regulation. The proposed
controller has been validated with simulation results.