Design Techniques and Implementation of Low Power High-Throughput Discrete Wavelet Transform Tilters for JPEG 2000 Standard

In this paper, the implementation of low power, high throughput convolutional filters for the one dimensional Discrete Wavelet Transform and its inverse are presented. The analysis filters have already been used for the implementation of a high performance DWT encoder [15] with minimum memory requirements for the JPEG 2000 standard. This paper presents the design techniques and the implementation of the convolutional filters included in the JPEG2000 standard for the forward and inverse DWT for achieving low-power operation, high performance and reduced memory accesses. Moreover, they have the ability of performing progressive computations so as to minimize the buffering between the decomposition and reconstruction phases. The experimental results illustrate the filters- low power high throughput characteristics as well as their memory efficient operation.

A 10 Giga VPN Accelerator Board for Trust Channel Security System

This paper proposes a VPN Accelerator Board (VPN-AB), a virtual private network (VPN) protocol designed for trust channel security system (TCSS). TCSS supports safety communication channel between security nodes in internet. It furnishes authentication, confidentiality, integrity, and access control to security node to transmit data packets with IPsec protocol. TCSS consists of internet key exchange block, security association block, and IPsec engine block. The internet key exchange block negotiates crypto algorithm and key used in IPsec engine block. Security Association blocks setting-up and manages security association information. IPsec engine block treats IPsec packets and consists of networking functions for communication. The IPsec engine block should be embodied by H/W and in-line mode transaction for high speed IPsec processing. Our VPN-AB is implemented with high speed security processor that supports many cryptographic algorithms and in-line mode. We evaluate a small TCSS communication environment, and measure a performance of VPN-AB in the environment. The experiment results show that VPN-AB gets a performance throughput of maximum 15.645Gbps when we set the IPsec protocol with 3DES-HMAC-MD5 tunnel mode.

Variable Guard Channels for Efficient Traffic Management

Guard channels improve the probability of successful handoffs by reserving a number of channels exclusively for handoffs. This concept has the risk of underutilization of radio spectrum due to the fact that fewer channels are granted to originating calls even if these guard channels are not always used, when originating calls are starving for the want of channels. The penalty is the reduction of total carried traffic. The optimum number of guard channels can help reduce this problem. This paper presents fuzzy logic based guard channel scheme wherein guard channels are reorganized on the basis of traffic density, so that guard channels are provided on need basis. This will help in incorporating more originating calls and hence high throughput of the radio spectrum

Simulations of Routing Protocols of Wireless Sensor Networks

Wireless Sensor Network is widely used in electronics. Wireless sensor networks are now used in many applications including military, environmental, healthcare applications, home automation and traffic control. We will study one area of wireless sensor networks, which is the routing protocol. Routing protocols are needed to send data between sensor nodes and the base station. In this paper, we will discuss two routing protocols, such as datacentric and hierarchical routing protocol. We will show the output of the protocols using the NS-2 simulator. This paper will compare the simulation output of the two routing protocol using Nam. We will simulate using Xgraph to find the throughput and delay of the protocol.

Distributed Relay Selection and Channel Choice in Cognitive Radio Network

In this paper, we study the cooperative communications where multiple cognitive radio (CR) transmit-receive pairs competitive maximize their own throughputs. In CR networks, the influences of primary users and the spectrum availability are usually different among CR users. Due to the existence of multiple relay nodes and the different spectrum availability, each CR transmit-receive pair should not only select the relay node but also choose the appropriate channel. For this distributed problem, we propose a game theoretic framework to formulate this problem and we apply a regret-matching learning algorithm which is leading to correlated equilibrium. We further formulate a modified regret-matching learning algorithm which is fully distributed and only use the local information of each CR transmit-receive pair. This modified algorithm is more practical and suitable for the cooperative communications in CR network. Simulation results show the algorithm convergence and the modified learning algorithm can achieve comparable performance to the original regretmatching learning algorithm.

Weighted k-Nearest-Neighbor Techniques for High Throughput Screening Data

The k-nearest neighbors (knn) is a simple but effective method of classification. In this paper we present an extended version of this technique for chemical compounds used in High Throughput Screening, where the distances of the nearest neighbors can be taken into account. Our algorithm uses kernel weight functions as guidance for the process of defining activity in screening data. Proposed kernel weight function aims to combine properties of graphical structure and molecule descriptors of screening compounds. We apply the modified knn method on several experimental data from biological screens. The experimental results confirm the effectiveness of the proposed method.

A Pipelined FSBM Hardware Architecture for HTDV-H.26x

In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Modeling and Analysis for Effective Capacity of a Cross-Layer Optimized Wireless Networks

New generation mobile communication networks have the ability of supporting triple play. In order that, Orthogonal Frequency Division Multiplexing (OFDM) access techniques have been chosen to enlarge the system ability for high data rates networks. Many of cross-layer modeling and optimization schemes for Quality of Service (QoS) and capacity of downlink multiuser OFDM system were proposed. In this paper, the Maximum Weighted Capacity (MWC) based resource allocation at the Physical (PHY) layer is used. This resource allocation scheme provides a much better QoS than the previous resource allocation schemes, while maintaining the highest or nearly highest capacity and costing similar complexity. In addition, the Delay Satisfaction (DS) scheduling at the Medium Access Control (MAC) layer, which allows more than one connection to be served in each slot is used. This scheduling technique is more efficient than conventional scheduling to investigate both of the number of users as well as the number of subcarriers against system capacity. The system will be optimized for different operational environments: the outdoor deployment scenarios as well as the indoor deployment scenarios are investigated and also for different channel models. In addition, effective capacity approach [1] is used not only for providing QoS for different mobile users, but also to increase the total wireless network's throughput.

Low Latency Routing Algorithm for Unmanned Aerial Vehicles Ad-Hoc Networks

In this paper, we proposed a new routing protocol for Unmanned Aerial Vehicles (UAVs) that equipped with directional antenna. We named this protocol Directional Optimized Link State Routing Protocol (DOLSR). This protocol is based on the well known protocol that is called Optimized Link State Routing Protocol (OLSR). We focused in our protocol on the multipoint relay (MPR) concept which is the most important feature of this protocol. We developed a heuristic that allows DOLSR protocol to minimize the number of the multipoint relays. With this new protocol the number of overhead packets will be reduced and the End-to-End delay of the network will also be minimized. We showed through simulation that our protocol outperformed Optimized Link State Routing Protocol, Dynamic Source Routing (DSR) protocol and Ad- Hoc On demand Distance Vector (AODV) routing protocol in reducing the End-to-End delay and enhancing the overall throughput. Our evaluation of the previous protocols was based on the OPNET network simulation tool.

An Adaptive ARQ – HARQ Method with Two RS Codes

In this paper we proposed multistage adaptive ARQ/HARQ/HARQ scheme. This method combines pure ARQ (Automatic Repeat reQuest) mode in low channel bit error rate and hybrid ARQ method using two different Reed-Solomon codes in middle and high error rate conditions. It follows, that our scheme has three stages. The main goal is to increase number of states in adaptive HARQ methods and be able to achieve maximum throughput for every channel bit error rate. We will prove the proposal by calculation and then with simulations in land mobile satellite channel environment. Optimization of scheme system parameters is described in order to maximize the throughput in the whole defined Signal-to- Noise Ratio (SNR) range in selected channel environment.

Joint Transmitter-Receiver Optimization for Bonded Wireline Communications

With the advent of DSL services, high data rates are now available over phone lines, yet higher rates are in demand. In this paper, we optimize the transmit filters that can be used over wireline channels. Results showing the bit error rates when optimized filters are used, and with a decision feedback equalizer (DFE) employed in the receiver, are given. We then show that significantly higher throughput can be achieved by modeling the channel as a multiple input multiple output (MIMO) channel. A receiver that employs a MIMO-DFE that deals jointly with several users is proposed and shown to provide significant improvement over the conventional DFE.

Parallel Branch and Bound Model Using Logarithmic Sampling (PBLS) for Symmetric Traveling Salesman Problem

Very Large and/or computationally complex optimization problems sometimes require parallel or highperformance computing for achieving a reasonable time for computation. One of the most popular and most complicate problems of this family is “Traveling Salesman Problem". In this paper we have introduced a Branch & Bound based algorithm for the solution of such complicated problems. The main focus of the algorithm is to solve the “symmetric traveling salesman problem". We reviewed some of already available algorithms and felt that there is need of new algorithm which should give optimal solution or near to the optimal solution. On the basis of the use of logarithmic sampling, it was found that the proposed algorithm produced a relatively optimal solution for the problem and results excellent performance as compared with the traditional algorithms of this series.

Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Increase Success by Decreasing Admission for Maths– Fairytale or Reality?

South Africa is facing a crisis with not being able to produce enough graduates in the scarce skills areas to sustain economic growth. The crisis is fuelled by a school system that does not produce enough potential students with Mathematics, Accounting and Science. Since the introduction of the new school curriculum in 2008, there is no longer an option to take pure maths on a standard grade level. Instead, only two mathematical subjects are offered: pure maths (which is on par with higher grade maths) and mathematical literacy. It is compulsory to take one or the other. As a result, lees student finishes Grade 12 with pure mathematics every year. This national problem needs urgent attention if South Africa is to make any headway in critical skills development as mathematics is a gateway to scarce skills professions. Higher education institutions initiated several initiatives in an attempt to address the above, including preparatory courses, bridging programmes and extended curricula with foundation provisions. In view of the above, and government policy directives to broaden access in the scarce skills areas to increase student throughput, foundation provision was introduced for Commerce and Information Technology programmes at the Vaal Triangle Campus (VTC) of North-West University (NWU) in 2010. Students enrolling for extended programmes do not comply with the minimum prerequisites for the normal programmes. The question then arises as to whether these programmes have the intended impact? This paper reports the results of a two year longitudinal study, tracking the first year academic achievement of the two cohorts of enrolments since 2010. The results provide valuable insight into the structuring of an extended programme and its potential impact.

Discrete Time Optimal Solution for the Connection Admission Control Problem

The Connection Admission Control (CAC) problem is formulated in this paper as a discrete time optimal control problem. The control variables account for the acceptance/ rejection of new connections and forced dropping of in-progress connections. These variables are constrained to meet suitable conditions which account for the QoS requirements (Link Availability, Blocking Probability, Dropping Probability). The performance index evaluates the total throughput. At each discrete time, the problem is solved as an integer-valued linear programming one. The proposed procedure was successfully tested against suitably simulated data.

Performance Analysis of HSDPA Systems using Low-Density Parity-Check (LDPC)Coding as Compared to Turbo Coding

HSDPA is a new feature which is introduced in Release-5 specifications of the 3GPP WCDMA/UTRA standard to realize higher speed data rate together with lower round-trip times. Moreover, the HSDPA concept offers outstanding improvement of packet throughput and also significantly reduces the packet call transfer delay as compared to Release -99 DSCH. Till now the HSDPA system uses turbo coding which is the best coding technique to achieve the Shannon limit. However, the main drawbacks of turbo coding are high decoding complexity and high latency which makes it unsuitable for some applications like satellite communications, since the transmission distance itself introduces latency due to limited speed of light. Hence in this paper it is proposed to use LDPC coding in place of Turbo coding for HSDPA system which decreases the latency and decoding complexity. But LDPC coding increases the Encoding complexity. Though the complexity of transmitter increases at NodeB, the End user is at an advantage in terms of receiver complexity and Bit- error rate. In this paper LDPC Encoder is implemented using “sparse parity check matrix" H to generate a codeword at Encoder and “Belief Propagation algorithm "for LDPC decoding .Simulation results shows that in LDPC coding the BER suddenly drops as the number of iterations increase with a small increase in Eb/No. Which is not possible in Turbo coding. Also same BER was achieved using less number of iterations and hence the latency and receiver complexity has decreased for LDPC coding. HSDPA increases the downlink data rate within a cell to a theoretical maximum of 14Mbps, with 2Mbps on the uplink. The changes that HSDPA enables includes better quality, more reliable and more robust data services. In other words, while realistic data rates are only a few Mbps, the actual quality and number of users achieved will improve significantly.

Hybridizing Genetic Algorithm with Biased Chance Local Search

This paper explores university course timetabling problem. There are several characteristics that make scheduling and timetabling problems particularly difficult to solve: they have huge search spaces, they are often highly constrained, they require sophisticated solution representation schemes, and they usually require very time-consuming fitness evaluation routines. Thus standard evolutionary algorithms lack of efficiency to deal with them. In this paper we have proposed a memetic algorithm that incorporates the problem specific knowledge such that most of chromosomes generated are decoded into feasible solutions. Generating vast amount of feasible chromosomes makes the progress of search process possible in a time efficient manner. Experimental results exhibit the advantages of the developed Hybrid Genetic Algorithm than the standard Genetic Algorithm.

Cloud Computing Initiative using Modified Ant Colony Framework

Scheduling of diversified service requests in distributed computing is a critical design issue. Cloud is a type of parallel and distributed system consisting of a collection of interconnected and virtual computers. It is not only the clusters and grid but also it comprises of next generation data centers. The paper proposes an initial heuristic algorithm to apply modified ant colony optimization approach for the diversified service allocation and scheduling mechanism in cloud paradigm. The proposed optimization method is aimed to minimize the scheduling throughput to service all the diversified requests according to the different resource allocator available under cloud computing environment.

Qualitative Parametric Comparison of Load Balancing Algorithms in Parallel and Distributed Computing Environment

Decrease in hardware costs and advances in computer networking technologies have led to increased interest in the use of large-scale parallel and distributed computing systems. One of the biggest issues in such systems is the development of effective techniques/algorithms for the distribution of the processes/load of a parallel program on multiple hosts to achieve goal(s) such as minimizing execution time, minimizing communication delays, maximizing resource utilization and maximizing throughput. Substantive research using queuing analysis and assuming job arrivals following a Poisson pattern, have shown that in a multi-host system the probability of one of the hosts being idle while other host has multiple jobs queued up can be very high. Such imbalances in system load suggest that performance can be improved by either transferring jobs from the currently heavily loaded hosts to the lightly loaded ones or distributing load evenly/fairly among the hosts .The algorithms known as load balancing algorithms, helps to achieve the above said goal(s). These algorithms come into two basic categories - static and dynamic. Whereas static load balancing algorithms (SLB) take decisions regarding assignment of tasks to processors based on the average estimated values of process execution times and communication delays at compile time, Dynamic load balancing algorithms (DLB) are adaptive to changing situations and take decisions at run time. The objective of this paper work is to identify qualitative parameters for the comparison of above said algorithms. In future this work can be extended to develop an experimental environment to study these Load balancing algorithms based on comparative parameters quantitatively.

Parallel Discrete Fourier Transform for Fast FIR Filtering Based on Overlapped-save Block Structure

To successfully provide a fast FIR filter with FTT algorithms, overlapped-save algorithms can be used to lower the computational complexity and achieve the desired real-time processing. As the length of the input block increases in order to improve the efficiency, a larger volume of zero padding will greatly increase the computation length of the FFT. In this paper, we use the overlapped block digital filtering to construct a parallel structure. As long as the down-sampling (or up-sampling) factor is an exact multiple lengths of the impulse response of a FIR filter, we can process the input block by using a parallel structure and thus achieve a low-complex fast FIR filter with overlapped-save algorithms. With a long filter length, the performance and the throughput of the digital filtering system will also be greatly enhanced.