Abstract: Short term electricity demand forecasts are required
by power utilities for efficient operation of the power grid. In a
competitive market environment, suppliers and large consumers also
require short term forecasts in order to estimate their energy
requirements in advance. Electricity demand is influenced (among
other things) by the day of the week, the time of year and special
periods and/or days such as Ramadhan, all of which must be
identified prior to modelling. This identification, known as day-type
identification, must be included in the modelling stage either by
segmenting the data and modelling each day-type separately or by
including the day-type as an input. Day-type identification is the
main focus of this paper. A Kohonen map is employed to identify the
separate day-types in Algerian data.
Abstract: In this paper an attempt has been made to correlate the usefulness of electrodes made through powder metallurgy (PM) in comparison with conventional copper electrode during electric discharge machining. Experimental results are presented on electric discharge machining of AISI D2 steel in kerosene with copper tungsten (30% Cu and 70% W) tool electrode made through powder metallurgy (PM) technique and Cu electrode. An L18 (21 37) orthogonal array of Taguchi methodology was used to identify the effect of process input factors (viz. current, duty cycle and flushing pressure) on the output factors {viz. material removal rate (MRR) and surface roughness (SR)}. It was found that CuW electrode (made through PM) gives high surface finish where as the Cu electrode is better for higher material removal rate.
Abstract: Fast delay estimation methods, as opposed to
simulation techniques, are needed for incremental performance
driven layout synthesis. On-chip inductive effects are becoming
predominant in deep submicron interconnects due to increasing clock
speed and circuit complexity. Inductance causes noise in signal
waveforms, which can adversely affect the performance of the circuit
and signal integrity. Several approaches have been put forward which
consider the inductance for on-chip interconnect modelling. But for
even much higher frequency, of the order of few GHz, the shunt
dielectric lossy component has become comparable to that of other
electrical parameters for high speed VLSI design. In order to cope up
with this effect, on-chip interconnect has to be modelled as
distributed RLCG line. Elmore delay based methods, although
efficient, cannot accurately estimate the delay for RLCG interconnect
line. In this paper, an accurate analytical delay model has been
derived, based on first and second moments of RLCG
interconnection lines. The proposed model considers both the effect
of inductance and conductance matrices. We have performed the
simulation in 0.18μm technology node and an error of as low as less
as 5% has been achieved with the proposed model when compared to
SPICE. The importance of the conductance matrices in interconnect
modelling has also been discussed and it is shown that if G is
neglected for interconnect line modelling, then it will result an delay
error of as high as 6% when compared to SPICE.