Abstract: The relationship between biodegradation and mechanical behavior is fundamental for studies of the application of cellulose acetate films as a possible material for biodegradable packaging. In this work, the biodegradation of cellulose acetate (CA) with DS 2.5 was analyzed in simulated soil. CA films were prepared by casting and buried in the simulated soil. Samples were taken monthly and analyzed, the total time of biodegradation was 6 months. To characterize the biodegradable CA, the DMA technique was employed. The main result showed that the time of exposure to the simulated soil affects the mechanical properties of the films and the values of crystallinity. By DMA analysis, it was possible to conclude that as the CA is biodegraded, its mechanical properties were altered, for example, storage modulus has increased with biodegradation and the modulus of loss has decreased. Analyzes of DSC, XRD, and FTIR were also carried out to characterize the biodegradation of CA, which corroborated with the results of DMA. The observation of the carbonyl band by FTIR and crystalline indices obtained by XRD were important to evaluate the degradation of CA during the exposure time.
Abstract: The next generation mobile communication systems i.e. fourth generation (4G) was developed to accommodate the quality of service and required data rate. This project focuses on multiple access technique proposed in 4G communication systems. It is attempted to demonstrate the IDMA (Interleave Division Multiple Access) technology. The basic principle of IDMA is that interleaver is different for each user whereas CDMA employs different signatures. IDMA inherits many advantages of CDMA such as robust against fading, easy cell planning; dynamic channel sharing and IDMA increase the spectral efficiency and reduce the receiver complexity. In this, performance of IDMA is analyzed using QC-LDPC coding scheme further it is compared with LDPC coding and at last BER is calculated and plotted in MATLAB.
Abstract: In this paper we propose a novel Run Time Interface
(RTI) technique to provide an efficient environment for MPI jobs on
the heterogeneous architecture of PARAM Padma. It suggests an
innovative, unified framework for the job management interface
system in parallel and distributed computing. This approach employs
proxy scheme. The implementation shows that the proposed RTI is
highly scalable and stable. Moreover RTI provides the storage access
for the MPI jobs in various operating system platforms and improve
the data access performance through high performance C-DAC
Parallel File System (C-PFS). The performance of the RTI is
evaluated by using the standard HPC benchmark suites and the
simulation results show that the proposed RTI gives good
performance on large scale supercomputing system.
Abstract: In this paper, we consider the analysis of the
acquisition process for a hybrid double-dwell system with antenna
diversity for DS-CDMA (direct sequence-code division multiple
access) using an adaptive threshold. Acquisition systems with a fixed
threshold value are unable to adapt to fast varying mobile
communications environments and may result in a high false alarm
rate, and/or low detection probability. Therefore, we propose an
adaptively varying threshold scheme through the use of a cellaveraging
constant false alarm rate (CA-CFAR) algorithm, which is
well known in the field of radar detection. We derive exact
expressions for the probabilities of detection and false alarm in
Rayleigh fading channels. The mean acquisition time of the system
under consideration is also derived. The performance of the system is
analyzed and compared to that of a hybrid single dwell system.
Abstract: This paper describes an efficient hardware implementation of a new technique for interfacing the data exchange between the microprocessor-based systems and the external devices. This technique, based on the use of software/hardware system and a reduced physical address, enlarges the interfacing capacity of the microprocessor-based systems, uses the Direct Memory Access (DMA) to increases the frequency of the new bus, and improves the speed of data exchange. While using this architecture in microprocessor-based system or in computer, the input of the hardware part of our system will be connected to the bus system, and the output, which is a new bus, will be connected to an external device. The new bus is composed of a data bus, a control bus and an address bus. A Xilinx Integrated Software Environment (ISE) 7.1i has been used for the programmable logic implementation.