Abstract: This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.
Abstract: The evolution of current modeling specifications gives rise to the problem of generating automated test cases from a variety of application tools. Past endeavours on behavioural testing of UML statecharts have not systematically leveraged the potential of existing graph theory for testing of objects. Therefore there exists a need for a simple, tool-independent, and effective method for automatic test generation. An architecture, codenamed ACUTE-J (Automated stateChart Unit Testing Engine for Java), for automating the unit test generation process is presented. A sequential approach for converting UML statechart diagrams to JUnit test classes is described, with the application of existing graph theory. Research byproducts such as a universal XML Schema and API for statechart-driven testing are also proposed. The result from a Java implementation of ACUTE-J is discussed in brief. The Chinese Postman algorithm is utilised as an illustration for a run-through of the ACUTE-J architecture.
Abstract: Conflicts identification among non-functional requirements is often identified intuitively which impairs conflict analysis practices. This paper proposes a new model to identify conflicts among non-functional requirements. The proposed model uses the matrix mechanism to identify the quality based conflicts among non-functional requirements. The potential conflicts are identified through the mapping of low level conflicting quality attributes to low level functionalities using the matrices. The proposed model achieves the identification of conflicts among product and process requirements, identifies false conflicts, decreases the documentation overhead, and maintains transparency of identified conflicts. The attributes are not concomitantly taken into account by current models in practice.
Abstract: In this paper, a new approach for design of a fully
differential second order current mode continuous-time sigma-delta
modulator is presented. For circuit implementation, square root
domain (SRD) translinear loop based on floating-gate MOS
transistors that operate in saturation region is employed. The
modulator features, low supply voltage, low power consumption
(8mW) and high dynamic range (55dB). Simulation results confirm
that this design is suitable for data converters.
Abstract: Magnesium is used implant material potentially for
non-toxicity to the human body. Due to the excellent
bio-compatibility, Mg alloys is applied to implants avoiding removal
second surgery. However, it is found commercial magnesium alloys
including aluminum has low corrosion resistance, resulting
subcutaneous gas bubbles and consequently the approach as
permanent bio-materials. Generally, Aluminum is known to pollution
substance, and it raises toxicity to nervous system. Therefore
especially Mg-35Zn-3Ca alloy is prepared for new biodegradable
materials in this study. And the pulsed power is used in
constant-current mode of DC power kinds of anodization. Based on
the aforementioned study, it examines corrosion resistance and
biocompatibility by effect of current and frequency variation. The
surface properties and thickness were compared using scanning
electronic microscopy. Corrosion resistance was assessed via
potentiodynamic polarization and the effect of oxide layer on the body
was assessed cell viability. Anodized Mg-35Zn-3Ca alloy has good
biocompatibility in vitro by current and frequency variation.
Abstract: Current mode circuits like current conveyors are
getting significant attention in current analog ICs design due to their
higher band-width, greater linearity, larger dynamic range, simpler
circuitry, lower power consumption and less chip area. The second
generation current controlled conveyor (CCCII) has the advantage of
electronic adjustability over the CCII i.e. in CCCII; adjustment of the
X-terminal intrinsic resistance via a bias current is possible. The
presented approach is based on the CMOS implementation of second
generation positive (CCCII+), negative (CCCII-) and dual Output
Current Controlled Conveyor (DOCCCII) and its application as
Universal filter. All the circuits have been designed and simulated
using 65nm CMOS technology model parameters on Cadence
Virtuoso / Spectre using 1V supply voltage. Various simulations have
been carried out to verify the linearity between output and input
ports, range of operation frequency, etc. The outcomes show good
agreement between expected and experimental results.
Abstract: In this paper, for the first time, a two-dimensional
(2D) analytical drain current model for sub-100 nm multi-layered
gate material engineered trapezoidal recessed channel (MLGMETRC)
MOSFET: a novel design is presented and investigated using
ATLAS and DEVEDIT device simulators, to mitigate the large gate
leakages and increased standby power consumption that arise due to
continued scaling of SiO2-based gate dielectrics. The twodimensional
(2D) analytical model based on solution of Poisson-s
equation in cylindrical coordinates, utilizing the cylindrical
approximation, has been developed which evaluate the surface
potential, electric field, drain current, switching metric: ION/IOFF
ratio and transconductance for the proposed design. A good
agreement between the model predictions and device simulation
results is obtained, verifying the accuracy of the proposed analytical
model.
Abstract: A universal current-mode biquad is described which
represents an economical variant of well-known KHN (Kerwin,
Huelsman, Newcomb) voltage-mode filter. The circuit consists of
two multiple-output OTAs and of two grounded capacitors. Utilizing
simple splitter of the input current and a pair of jumpers, all the basic
2nd-order transfer functions can be implemented. The principle is
verified by Spice simulation on the level of a CMOS structure of
OTAs.
Abstract: Timing driven physical design, synthesis, and
optimization tools need efficient closed-form delay models for
estimating the delay associated with each net in an integrated circuit
(IC) design. The total number of nets in a modern IC design has
increased dramatically and exceeded millions. Therefore efficient
modeling of interconnection is needed for high speed IC-s. This
paper presents closed–form expressions for RC and RLC
interconnection trees in current mode signaling, which can be
implemented in VLSI design tool. These analytical model
expressions can be used for accurate calculation of delay after the
design clock tree has been laid out and the design is fully routed.
Evaluation of these analytical models is several orders of magnitude
faster than simulation using SPICE.
Abstract: To extract the important physiological factors related to
diabetes from an oral glucose tolerance test (OGTT) by mathematical
modeling, highly informative but convenient protocols are required.
Current models require a large number of samples and extended
period of testing, which is not practical for daily use. The purpose
of this study is to make model assessments possible even from a
reduced number of samples taken over a relatively short period.
For this purpose, test values were extrapolated using a support
vector machine. A good correlation was found between reference and
extrapolated values in evaluated 741 OGTTs. This result indicates
that a reduction in the number of clinical test is possible through a
computational approach.
Abstract: In this paper, we have developed an explicit analytical
drain current model comprising surface channel potential and
threshold voltage in order to explain the advantages of the proposed
Gate Stack Double Diffusion (GSDD) MOSFET design over the
conventional MOSFET with the same geometric specifications that
allow us to use the benefits of the incorporation of the high-k layer
between the oxide layer and gate metal aspect on the immunity of the
proposed design against the self-heating effects. In order to show the
efficiency of our proposed structure, we propose the simulation of the
power chopper circuit. The use of the proposed structure to design a
power chopper circuit has showed that the (GSDD) MOSFET can
improve the working of the circuit in terms of power dissipation and
self-heating effect immunity. The results so obtained are in close
proximity with the 2D simulated results thus confirming the validity
of the proposed model.
Abstract: The paper presents a simple and an accurate formula
that has been developed for the conduction angle (δ) of a single
phase half-wave or full-wave controlled rectifier with RL load. This
formula can be also used for calculating the conduction angle (δ) in
case of A.C. voltage regulator with inductive load under
discontinuous current mode. The simulation results shows that the
conduction angle calculated from the developed formula agree very
well with that obtained from the exact solution arrived from the
iterative method. Applying the developed formula can reduce the
computational time and reduce the time for manual classroom
calculation. In addition, the proposed formula is attractive for real
time implementations.
Abstract: In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].