Abstract: In this paper, a new approach for design of a fully
differential second order current mode continuous-time sigma-delta
modulator is presented. For circuit implementation, square root
domain (SRD) translinear loop based on floating-gate MOS
transistors that operate in saturation region is employed. The
modulator features, low supply voltage, low power consumption
(8mW) and high dynamic range (55dB). Simulation results confirm
that this design is suitable for data converters.
Abstract: This paper presents a new true RMS-to-DC converter
circuit based on a square-root-domain squarer/divider. The circuit is
designed by employing up-down translinear loop and using of
MOSFET transistors that operate in strong inversion saturation
region. The converter offer advantages of two-quadrant input current,
low circuit complexity, low supply voltage (1.2V) and immunity
from the body effect. The circuit has been simulated by HSPICE.
The simulation results are seen to conform to the theoretical analysis
and shows benefits of the proposed circuit.
Abstract: This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.
Abstract: Versatile dual-mode class-AB CMOS four-quadrant
analog multiplier circuit is presented. The dual translinear loops and
current mirrors are the basic building blocks in realization scheme.
This technique provides; wide dynamic range, wide-bandwidth response
and low power consumption. The major advantages of this
approach are; its has single ended inputs; since its input is dual translinear
loop operate in class-AB mode which make this multiplier
configuration interesting for low-power applications; current multiplying,
voltage multiplying, or current and voltage multiplying can
be obtainable with balanced input. The simulation results of versatile
analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth
of about 19MHz, a maximum power consumption of 0.46mW,
and temperature compensated. Operation of versatile analog multiplier
was also confirmed through an experiment using CMOS transistor
array.