Abstract: This paper describes I²C Slave implementation using
I²C master obtained from the OpenCores website. This website
provides free Verilog and VHDL Codes to users. The design
implementation for the I²C slave is in Verilog Language and uses
EDA tools for ASIC design known as ModelSim from Mentor
Graphic. This tool is used for simulation and verification purposes.
Common application for this I²C Master-Slave integration is also
included. This paper also addresses the advantages and limitations of
the said design.