I²C Master-Slave Integration

This paper describes I²C Slave implementation using I²C master obtained from the OpenCores website. This website provides free Verilog and VHDL Codes to users. The design implementation for the I²C slave is in Verilog Language and uses EDA tools for ASIC design known as ModelSim from Mentor Graphic. This tool is used for simulation and verification purposes. Common application for this I²C Master-Slave integration is also included. This paper also addresses the advantages and limitations of the said design.

Authors:

• Rozita Borhan
• Lam Kien Sieng

Keywords:

• I²C
• master
• opencores
• slave
• verilog
• verification.

References:

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Rev：1.0 2004-7-28 , 2004
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http://vishay.com, 2011, page 12.
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Design”2007
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http://components.about.com/od/Theory/a/Overview-Of-I2c.htm, date
visited: 25 April 2015.
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Interfaced With RAM Using VHDL”, Journal of Engineering Research
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