Abstract: Understanding and using the functional paradigm is a challenge for many programmers. Looking for logical errors in code may take a lot of a developer’s time when a program grows in size. In order to facilitate both processes, this paper presents HaskellFL, a tool that uses fault localization techniques to locate a logical error in Haskell code. The Haskell subset used in this work is sufficiently expressive for those studying Functional Programming to get immediate help debugging their code and to answer questions about key concepts associated with the functional paradigm. HaskellFL was tested against Functional Programming assignments submitted by students enrolled at the Functional Programming class at the Federal University of Minas Gerais and against exercises from the Exercism Haskell track that are publicly available in GitHub. This work also evaluated the effectiveness of two fault localization techniques, Tarantula and Ochiai, in the Haskell context. Furthermore, the EXAM score was chosen to evaluate the tool’s effectiveness, and results showed that HaskellFL reduced the effort needed to locate an error for all tested scenarios. The results also showed that the Ochiai method was more effective than Tarantula.
Abstract: In general, state-of-the-art Data Acquisition Systems
(DAQ) in high energy physics experiments must satisfy high
requirements in terms of reliability, efficiency and data rate capability.
This paper presents the development and deployment of a debugging
tool named DAQ Debugger for the intelligent, FPGA-based Data
Acquisition System (iFDAQ) of the COMPASS experiment at CERN.
Utilizing a hardware event builder, the iFDAQ is designed to be
able to readout data at the average maximum rate of 1.5 GB/s of
the experiment. In complex softwares, such as the iFDAQ, having
thousands of lines of code, the debugging process is absolutely
essential to reveal all software issues. Unfortunately, conventional
debugging of the iFDAQ is not possible during the real data taking.
The DAQ Debugger is a tool for identifying a problem, isolating
the source of the problem, and then either correcting the problem
or determining a way to work around it. It provides the layer
for an easy integration to any process and has no impact on the
process performance. Based on handling of system signals, the
DAQ Debugger represents an alternative to conventional debuggers
provided by most integrated development environments. Whenever
problem occurs, it generates reports containing all necessary
information important for a deeper investigation and analysis. The
DAQ Debugger was fully incorporated to all processes in the iFDAQ
during the run 2016. It helped to reveal remaining software issues
and improved significantly the stability of the system in comparison
with the previous run. In the paper, we present the DAQ Debugger
from several insights and discuss it in a detailed way.
Abstract: A detailed analysis has been performed for several schemes of Gas Turbine Wheels production based on additive and powder technologies including metal, ceramic, and stereolithography 3-D printing. During the process of development and debugging of gas turbine engine components, different versions of these components must be manufactured and tested. Cooled blades of the turbine are among of these components. They are usually produced by traditional casting methods. This method requires long and costly design and manufacture of casting molds. Moreover, traditional manufacturing methods limit the design possibilities of complex critical parts of engine, so capabilities of Powder Metallurgy Techniques (PMT) were analyzed to manufacture the turbine wheel with air-cooled blades. PMT dramatically reduce time needed for such production and allow creating new complex design solutions aimed at improving the technical characteristics of the engine: improving fuel efficiency and environmental performance, increasing reliability, and reducing weight. To accelerate and simplify the blades manufacturing process, several options based on additive technologies were used. The options were implemented in the form of various casting equipment for the manufacturing of blades. Methods of powder metallurgy were applied for connecting the blades with the disc. The optimal production scheme and a set of technologies for the manufacturing of blades and turbine wheel and other parts of the engine can be selected on the basis of the options considered.
Abstract: Modern experiments in high energy physics impose
great demands on the reliability, the efficiency, and the data rate
of Data Acquisition Systems (DAQ). This contribution focuses on
the development and deployment of the new communication library
DIALOG for the intelligent, FPGA-based Data Acquisition System
(iFDAQ) of the COMPASS experiment at CERN. The iFDAQ
utilizing a hardware event builder is designed to be able to readout
data at the maximum rate of the experiment. The DIALOG library is a
communication system both for distributed and mixed environments,
it provides a network transparent inter-process communication layer.
Using the high-performance and modern C++ framework Qt and its
Qt Network API, the DIALOG library presents an alternative to
the previously used DIM library. The DIALOG library was fully
incorporated to all processes in the iFDAQ during the run 2016.
From the software point of view, it might be considered as a
significant improvement of iFDAQ in comparison with the previous
run. To extend the possibilities of debugging, the online monitoring
of communication among processes via DIALOG GUI is a desirable
feature. In the paper, we present the DIALOG library from several
insights and discuss it in a detailed way. Moreover, the efficiency
measurement and comparison with the DIM library with respect to
the iFDAQ requirements is provided.
Abstract: Software Defined Networking (SDN) is a new norm of networks. It is designed to facilitate the way of managing, measuring, debugging and controlling the network dynamically, and to make it suitable for the modern applications. Generally, measurement methods can be divided into two categories: Active and passive methods. Active measurement method is employed to inject test packets into the network in order to monitor their behaviour (ping tool as an example). Meanwhile the passive measurement method is used to monitor the traffic for the purpose of deriving measurement values. The measurement methods, both active and passive, are useful for the collection of traffic statistics, and monitoring of the network traffic. Although there has been a work focusing on measuring traffic statistics in SDN environment, it was only meant for measuring packets and bytes rates for non-web traffic. In this study, a feasible method will be designed to measure the number of packets and bytes in a certain time, and facilitate obtaining statistics for both web traffic and non-web traffic. Web traffic refers to HTTP requests that use application layer; while non-web traffic refers to ICMP and TCP requests. Thus, this work is going to be more comprehensive than previous works. With a developed module on POX OpenFlow controller, information will be collected from each active flow in the OpenFlow switch, and presented on Command Line Interface (CLI) and wireshark interface. Obviously, statistics that will be displayed on CLI and on wireshark interfaces include type of protocol, number of bytes and number of packets, among others. Besides, this module will show the number of flows added to the switch whenever traffic is generated from and to hosts in the same statistics list. In order to carry out this work effectively, our Python module will send a statistics request message to the switch requesting its current ports and flows statistics in every five seconds; while the switch will reply with the required information in a message called statistics reply message. Thus, POX controller will be notified and updated with any changes could happen in the entire network in a very short time. Therefore, our aim of this study is to prepare a list for the important statistics elements that are collected from the whole network, to be used for any further researches; particularly, those that are dealing with the detection of the network attacks that cause a sudden rise in the number of packets and bytes like Distributed Denial of Service (DDoS).
Abstract: Polymorphism is one of the main pillars of objectoriented
paradigm. It induces hidden forms of class dependencies
which may impact software quality, resulting in higher cost factor for
comprehending, debugging, testing, and maintaining the software. In
this paper, a new cognitive complexity metric called Cognitive
Weighted Polymorphism Factor (CWPF) is proposed. Apart from the
software structural complexity, it includes the cognitive complexity
on the basis of type. The cognitive weights are calibrated based on 27
empirical studies with 120 persons. A case study and experimentation
of the new software metric shows positive results. Further, a
comparative study is made and the correlation test has proved that
CWPF complexity metric is a better, more comprehensive, and more
realistic indicator of the software complexity than Abreu’s
Polymorphism Factor (PF) complexity metric.
Abstract: The legends about “user-friendly” and “easy-to-use”
birotical tools (computer-related office tools) have been spreading
and misleading end-users. This approach has led us to the extremely
high number of incorrect documents, causing serious financial losses
in the creating, modifying, and retrieving processes. Our research
proved that there are at least two sources of this underachievement:
(1) The lack of the definition of the correctly edited, formatted
documents. Consequently, end-users do not know whether their
methods and results are correct or not. They are not aware of their
ignorance. They are so ignorant that their ignorance does not allow
them to realize their lack of knowledge. (2) The end-users’ problem
solving methods. We have found that in non-traditional programming
environments end-users apply, almost exclusively, surface approach
metacognitive methods to carry out their computer related activities,
which are proved less effective than deep approach methods.
Based on these findings we have developed deep approach
methods which are based on and adapted from traditional
programming languages. In this study, we focus on the most popular
type of birotical documents, the text based documents. We have
provided the definition of the correctly edited text, and based on this
definition, adapted the debugging method known in programming.
According to the method, before the realization of text editing, a
thorough debugging of already existing texts and the categorization
of errors are carried out. With this method in advance to real text
editing users learn the requirements of text based documents and also
of the correctly formatted text.
The method has been proved much more effective than the
previously applied surface approach methods. The advantages of the
method are that the real text handling requires much less human and
computer sources than clicking aimlessly in the GUI (Graphical User
Interface), and the data retrieval is much more effective than from
error-prone documents.
Abstract: The aim of this study was to design and simulate a
particular type of Asynchronous State Machine (ASM), namely a
‘traffic light controller’ (TLC), operated at a frequency of 0.5 Hz.
The design task involved two main stages: firstly, designing a 4-bit
binary counter using J-K flip flops as the timing signal and,
subsequently, attaining the digital logic by deploying ASM design
process. The TLC was designed such that it showed a sequence of
three different colours, i.e. red, yellow and green, corresponding to
set thresholds by deploying the least number of AND, OR and NOT
gates possible. The software Multisim was deployed to design such
circuit and simulate it for circuit troubleshooting in order for it to
display the output sequence of the three different colours on the
traffic light in the correct order. A clock signal, an asynchronous 4-
bit binary counter that was designed through the use of J-K flip flops
along with an ASM were used to complete this sequence, which was
programmed to be repeated indefinitely. Eventually, the circuit was
debugged and optimized, thus displaying the correct waveforms of
the three outputs through the logic analyser. However, hazards
occurred when the frequency was increased to 10 MHz. This was
attributed to delays in the feedback being too high.
Abstract: A packet analyzer is a tool for debugging sensor
network systems and is convenient for developers. In this paper, we
introduce a new packet analyzer based on an embedded system. The
proposed packet analyzer is compatible with IEEE 802.15.4, which is
suitable for the wireless communication standard for sensor networks,
and is available for remote control by adopting a server-client scheme
based on the Ethernet interface. To confirm the operations of the
packet analyzer, we have developed two types of sensor nodes based
on PIC4620 and ATmega128L microprocessors and tested the
functions of the proposed packet analyzer by obtaining the packets
from the sensor nodes.
Abstract: Program slicing is the task of finding all statements in
a program that directly or indirectly influence the value of a variable
occurrence. The set of statements that can affect the value of a
variable at some point in a program is called a program backward
slice. In several software engineering applications, such as program
debugging and measuring program cohesion and parallelism, several
slices are computed at different program points. The existing
algorithms for computing program slices are introduced to compute a
slice at a program point. In these algorithms, the program, or the
model that represents the program, is traversed completely or
partially once. To compute more than one slice, the same algorithm
is applied for every point of interest in the program. Thus, the same
program, or program representation, is traversed several times.
In this paper, an algorithm is introduced to compute all forward
static slices of a computer program by traversing the program
representation graph once. Therefore, the introduced algorithm is
useful for software engineering applications that require computing
program slices at different points of a program. The program
representation graph used in this paper is called Program Dependence
Graph (PDG).
Abstract: This paper proposes a novel methodology for enabling
debugging and tracing of production web applications without
affecting its normal flow and functionality. This method of debugging
enables developers and maintenance engineers to replace a set of
existing resources such as images, server side scripts, cascading
style sheets with another set of resources per web session. The new
resources will only be active in the debug session and other sessions
will not be affected. This methodology will help developers in tracing
defects, especially those that appear only in production environments
and in exploring the behaviour of the system. A realization of the
proposed methodology has been implemented in Java.
Abstract: Concurrency and synchronization are becoming big
issues as every new PC comes with multi-core processors. A major
reason for Object-Oriented Programming originally was to enable
easier reuse: encode your algorithm into a class and thoroughly
debug it, then you can reuse the class again and again. However,
when we get to concurrency and synchronization, this is often not
possible. Thread-safety issues means that synchronization constructs
need to be entangled into every class involved. We contributed a
detailed literature review of issues and challenges in concurrent
programming and present a methodology that uses the Aspect-
Oriented paradigm to address this problem. Aspects will allow us to
extract the synchronization concerns as schemes to be “weaved in"
later into the main code. This allows the aspects to be separately
tested and verified. Hence, the functional components can be weaved
with reusable synchronization schemes that are robust and scalable.
Abstract: Program slicing is the task of finding all statements in a program that directly or indirectly influence the value of a variable occurrence. The set of statements that can affect the value of a variable at some point in a program is called a program slice. In several software engineering applications, such as program debugging and measuring program cohesion and parallelism, several slices are computed at different program points. In this paper, algorithms are introduced to compute all backward and forward static slices of a computer program by traversing the program representation graph once. The program representation graph used in this paper is called Program Dependence Graph (PDG). We have conducted an experimental comparison study using 25 software modules to show the effectiveness of the introduced algorithm for computing all backward static slices over single-point slicing approaches in computing the parallelism and functional cohesion of program modules. The effectiveness of the algorithm is measured in terms of time execution and number of traversed PDG edges. The comparison study results indicate that using the introduced algorithm considerably saves the slicing time and effort required to measure module parallelism and functional cohesion.
Abstract: IEEE has designed 802.11i protocol to address the
security issues in wireless local area networks. Formal analysis is
important to ensure that the protocols work properly without having
to resort to tedious testing and debugging which can only show the
presence of errors, never their absence. In this paper, we present
the formal verification of an abstract protocol model of 802.11i.
We translate the 802.11i protocol into the Strand Space Model and
then prove the authentication property of the resulting model using
the Strand Space formalism. The intruder in our model is imbued
with powerful capabilities and repercussions to possible attacks are
evaluated. Our analysis proves that the authentication of 802.11i is
not compromised in the presented model. We further demonstrate
how changes in our model will yield a successful man-in-the-middle
attack.
Abstract: The overlay approach has been widely used by many service providers for Traffic Engineering (TE) in large Internet backbones. In the overlay approach, logical connections are set up between edge nodes to form a full mesh virtual network on top of the physical topology. IP routing is then run over the virtual network. Traffic engineering objectives are achieved through carefully routing logical connections over the physical links. Although the overlay approach has been implemented in many operational networks, it has a number of well-known scaling issues. This paper proposes a new approach to achieve traffic engineering without full-mesh overlaying with the help of integrated approach and equal subset split method. Traffic engineering needs to determine the optimal routing of traffic over the existing network infrastructure by efficiently allocating resource in order to optimize traffic performance on an IP network. Even though constraint-based routing [1] of Multi-Protocol Label Switching (MPLS) is developed to address this need, since it is not widely tested or debugged, Internet Service Providers (ISPs) resort to TE methods under Open Shortest Path First (OSPF), which is the most commonly used intra-domain routing protocol. Determining OSPF link weights for optimal network performance is an NP-hard problem. As it is not possible to solve this problem, we present a subset split method to improve the efficiency and performance by minimizing the maximum link utilization in the network via a small number of link weight modifications. The results of this method are compared against results of MPLS architecture [9] and other heuristic methods.
Abstract: WebGL is typically used with web browsers. In this
paper, we represent a standalone WebGL execution environment,
where the original WebGL source codes show the same result to those
of WebGL-capable web browsers. This standalone environment
enables us to run WebGL programs without web browsers and/or
internet connections. Our implementation shows the same rendering
results with typical web browser outputs. This standalone environment
is suitable for low-tier devices and/or debugging purposes.
Abstract: According to the density of the chips, designers are
trying to put so any facilities of computational and storage on single
chips. Along with the complexity of computational and storage
circuits, the designing, testing and debugging become more and more
complex and expensive. So, hardware design will be built by using
very high speed hardware description language, which is more
efficient and cost effective. This paper will focus on the
implementation of 32-bit ALU design based on Verilog hardware
description language. Adder and subtracter operate correctly on both
unsigned and positive numbers. In ALU, addition takes most of the
time if it uses the ripple-carry adder. The general strategy for
designing fast adders is to reduce the time required to form carry
signals. Adders that use this principle are called carry look- ahead
adder. The carry look-ahead adder is to be designed with combination
of 4-bit adders. The syntax of Verilog HDL is similar to the C
programming language. This paper proposes a unified approach to
ALU design in which both simulation and formal verification can
co-exist.
Abstract: In spite of all advancement in software testing,
debugging remains a labor-intensive, manual, time consuming, and
error prone process. A candidate solution to enhance debugging
process is to fuse it with testing process. To achieve this integration,
a possible solution may be categorizing common software tests and
errors followed by the effort on fixing the errors through general
solutions for each test/error pair. Our approach to address this issue is
based on Christopher Alexander-s pattern and pattern language
concepts. The patterns in this language are grouped into three major
sections and connect the three concepts of test, error, and debug.
These patterns and their hierarchical relationship shape a pattern
language that introduces a solution to solve software errors in a
known testing context.
Finally, we will introduce our developed framework ADE as a
sample implementation to support a pattern of proposed language,
which aims to automate the whole process of evolving software
design via evolutionary methods.
Abstract: In this paper, we propose a hardware and software
design method for automotive Electronic Control Units (ECU)
considering the functional safety. The proposed ECU is considered for
the application to Electro-Mechanical Actuator systems and the
validity of the design method is shown by the application to the
Electro-Mechanical Brake (EMB) control system which is used as a
brake actuator in Brake-By-Wire (BBW) systems. The importance of a
functional safety-based design approach to EMB ECU design has been
emphasized because of its safety-critical functions, which are executed
with the aid of many electric actuators, sensors, and application
software. Based on hazard analysis and risk assessment according to
ISO26262, the EMB system should be ASIL-D-compliant, the highest
ASIL level. To this end, an external signature watchdog and an
Infineon 32-bit microcontroller TriCore are used to reduce risks
considering common-cause hardware failure. Moreover, a software
design method is introduced for implementing functional
safety-oriented monitoring functions based on an asymmetric dual
core architecture considering redundancy and diversity. The validity
of the proposed ECU design approach is verified by using the EMB
Hardware-In-the-Loop (HILS) system, which consists of the EMB
assembly, actuator ECU, a host PC, and a few debugging devices.
Furthermore, it is shown that the existing sensor fault tolerant control
system can be used more effectively for mitigating the effects of
hardware and software faults by applying the proposed ECU design
method.
Abstract: The Programmable Logic Controller (PLC) plays a
vital role in automation and process control. Grafcet is used for
representing the control logic, and traditional programming
languages are used for describing the pure algorithms. Grafcet is used
for dividing the process to be automated in elementary sequences that
can be easily implemented. Each sequence represent a step that has
associated actions programmed using textual or graphical languages
after case. The programming task is simplified by using a set of
subroutines that are used in several steps. The paper presents an
example of implementation for a punching machine for sheets and
plates. The use the graphical languages the programming of a
complex sequential process is a necessary solution. The state of
Grafcet can be used for debugging and malfunction determination.
The use of the method combined with a set of knowledge acquisition
for process application reduces the downtime of the machine and
improve the productivity.