Abstract: Duplicated region detection is a technical method to
expose copy-paste forgeries on digital images. Copy-paste is one
of the common types of forgeries to clone portion of an image
in order to conceal or duplicate special object. In this type of
forgery detection, extracting robust block feature and also high
time complexity of matching step are two main open problems.
This paper concentrates on computational time and proposes a local
block matching algorithm based on block clustering to enhance time
complexity. Time complexity of the proposed algorithm is formulated
and effects of two parameter, block size and number of cluster, on
efficiency of this algorithm are considered. The experimental results
and mathematical analysis demonstrate this algorithm is more costeffective
than lexicographically algorithms in time complexity issue
when the image is complex.
Abstract: Internet application in China has maintained a constant
development tendency in the past decade. China is now one of the
most populous countries in terms of internet user population. While
offering enormous opportunities, the dramatic digitalization also
brings about a series of challenges that demand urgent attention.
Digital divide is one of the challenges that affect China as well as other
countries in the world. This paper examines digital divide in the
Chinese context from the perspective of development communication.
Through a case study of a rural township under the backdrop of the
rapid internet development in China, the paper discusses the
economic, psychological and cultural roots of digital divide; and
explores development communication strategies addressing the roots
of digital divide. It is argued that development communication must be
responsive to the potentialities and preferences of the specific society
and serve the purposes of participation and sustainability.
Abstract: Implemented 5-bit 125-MS/s successive
approximation register (SAR) analog to digital converter (ADC) on
FPGA is presented in this paper.The design and modeling of a high
performance SAR analog to digital converter are based on monotonic
capacitor switching procedure algorithm .Spartan 3 FPGA is chosen
for implementing SAR analog to digital converter algorithm. SAR
VHDL program writes in Xilinx and modelsim uses for showing
results.
Abstract: People nowadays love to travel around the world.
Regardless of their location and time, they especially Muslims still need to perform their five times prayer. Normally for travelers, they
need to bring maps, compass and for Muslim, they even have to bring Qibla pointer when they travel. It is slightly difficult to
determine the Qibla direction and to know the time for each prayer. In this paper we present a new electronic device called Universal Qibla and Prayer Time Finder to locate the Qibla direction and to determine each prayer time based on the current user-s location. This device use PIC microcontroller equipped with digital compass and
Global Positioning System (GPS) where it will display the exact Qibla direction and prayer time automatically at any place in the world. This device is reliable, user friendly and accurate in
determining the Qibla direction and prayer time.
Abstract: Through the analysis of the process digital design
based on digital mockup, the fact indicates that a distributed
cooperative supporting environment is the foundation conditions to
adopt design approach based on DMU. Data access authorization is
concerned firstly because the value and sensitivity of the data for the
enterprise. The access control for administrators is often rather weak
other than business user. So authors established an enhanced system to
avoid the administrators accessing the engineering data by potential
approach and without authorization. Thus the data security is
improved.
Abstract: Compaction testing methods allow at-speed detecting
of errors while possessing low cost of implementation. Owing to this
distinctive feature, compaction methods have been widely used for
built-in testing, as well as external testing. In the latter case, the
bandwidth requirements to the automated test equipment employed
are relaxed which reduces the overall cost of testing. Concurrent
compaction testing methods use operational signals to detect
misbehavior of the device under test and do not require input test
stimuli. These methods have been employed for digital systems only.
In the present work, we extend the use of compaction methods for
concurrent testing of analog-to-digital converters. We estimate
tolerance bounds for the result of compaction and evaluate the
aliasing rate.
Abstract: Random Access Memory (RAM) is an important
device in computer system. It can represent the snapshot on how the
computer has been used by the user. With the growth of its
importance, the computer memory has been an issue that has been
discussed in digital forensics. A number of tools have been developed
to retrieve the information from the memory. However, most of the
tools have their limitation in the ability of retrieving the important
information from the computer memory. Hence, this paper is aimed
to discuss the limitation and the setback for two main techniques such
as process signature search and process enumeration. Then, a new
hybrid approach will be presented to minimize the setback in both
individual techniques. This new approach combines both techniques
with the purpose to retrieve the information from the process block
and other objects in the computer memory. Nevertheless, the basic
theory in address translation for x86 platforms will be demonstrated
in this paper.
Abstract: In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.
Abstract: Evolvable hardware (EHW) is a developing field that
applies evolutionary algorithm (EA) to automatically design circuits,
antennas, robot controllers etc. A lot of research has been done in this
area and several different EAs have been introduced to tackle
numerous problems, as scalability, evolvability etc. However every
time a specific EA is chosen for solving a particular task, all its
components, such as population size, initialization, selection
mechanism, mutation rate, and genetic operators, should be selected
in order to achieve the best results. In the last three decade the
selection of the right parameters for the EA-s components for solving
different “test-problems" has been investigated. In this paper the
behaviour of mutation rate for designing logic circuits, which has not
been done before, has been deeply analyzed. The mutation rate for an
EHW system modifies the number of inputs of each logic gates, the
functionality (for example from AND to NOR) and the connectivity
between logic gates. The behaviour of the mutation has been
analyzed based on the number of generations, genotype redundancy
and number of logic gates for the evolved circuits. The experimental
results found provide the behaviour of the mutation rate during
evolution for the design and optimization of simple logic circuits.
The experimental results propose the best mutation rate to be used for
designing combinational logic circuits. The research presented is
particular important for those who would like to implement a
dynamic mutation rate inside the evolutionary algorithm for evolving
digital circuits. The researches on the mutation rate during the last 40
years are also summarized.
Abstract: This paper addresses an efficient technique to embed and detect digital fingerprint code. Orthogonal modulation method is a straightforward and widely used approach for digital fingerprinting but shows several limitations in computational cost and signal efficiency. Coded modulation method can solve these limitations in theory. However it is difficult to perform well in practice if host signals are not available during tracing colluders, other kinds of attacks are applied, and the size of fingerprint code becomes large. In this paper, we propose a hybrid modulation method, in which the merits of or-thogonal modulation and coded modulation method are combined so that we can achieve low computational cost and high signal efficiency. To analyze the performance, we design a new fingerprint code based on GD-PBIBD theory and modulate this code into images by our method using spread-spectrum watermarking on frequency domain. The results show that the proposed method can efficiently handle large fingerprint code and trace colluders against averaging attacks.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: The simulation of external aerodynamics is one of the most challenging and important automotive CFD applications. With the rapid developments of digital computers, CFD is used as a practical tool in modern fluid dynamics research. It integrates fluid mechanics disciplines, mathematics and computer science. In this study, two different types of simulations were made, one for the flow around a simplified high speed passenger car with a rear-spoiler and the other for the flow without a rear-spoiler. The standard k-ε model is selected to numerically simulate the external flow field of the simplified Camry model with or without a rear-spoiler. Through an analysis of the simulation results, a new rear spoiler is designed and it shows a mild reduction of the vehicle aerodynamics drag. This leads to less vehicle fuel consumption on the road.
Abstract: This paper presents an intelligent speed control
system based on fuzzy logic for a voltage source PWM inverter-fed
indirect vector controlled induction motor drive. Traditional indirect
vector control system of induction motor introduces conventional PI
regulator in outer speed loop; it is proved that the low precision of the
speed regulator debases the performance of the whole system. To
overcome this problem, replacement of PI controller by an intelligent
controller based on fuzzy set theory is proposed. The performance of
the intelligent controller has been investigated through digital
simulation using MATLAB-SIMULINK package for different
operating conditions such as sudden change in reference speed and
load torque. The simulation results demonstrate that the performance
of the proposed controller is better than that of the conventional PI
controller.
Abstract: The evolutionary design of electronic circuits, or
evolvable hardware, is a discipline that allows the user to
automatically obtain the desired circuit design. The circuit
configuration is under the control of evolutionary algorithms. Several
researchers have used evolvable hardware to design electrical
circuits. Every time that one particular algorithm is selected to carry
out the evolution, it is necessary that all its parameters, such as
mutation rate, population size, selection mechanisms etc. are tuned in
order to achieve the best results during the evolution process. This
paper investigates the abilities of evolution strategy to evolve digital
logic circuits based on programmable logic array structures when
different mutation rates are used. Several mutation rates (fixed and
variable) are analyzed and compared with each other to outline the
most appropriate choice to be used during the evolution of
combinational logic circuits. The experimental results outlined in this
paper are important as they could be used by every researcher who
might need to use the evolutionary algorithm to design digital logic
circuits.
Abstract: In this paper application of artificial intelligence for
baby and children caring is studied. Then a new idea for injury
prevention and safety announcement is presented by using digital
image processing. The paper presents the structure of the proposed
system. The system determines the possibility of the dangers for
children and babies in yards, gardens and swimming pools or etc. In
the presented idea, multi camera System is used and receiver videos
are processed to find the hazardous areas then the entrance of
children and babies in the determined hazardous areas are analyzed.
In this condition the system does the programmed action capture,
produce alarm or tone or send message.
Abstract: Truncated multiplier is a good candidate for digital
signal processing (DSP) applications including finite impulse
response (FIR) and discrete cosine transform (DCT). Through
truncated multiplier a significant reduction in Field Programmable
Gate Array (FPGA) resources can be achieved. This paper presents
for the first time a comparison of resource utilization of Spartan-3AN
and Virtex-5 implementation of standard and truncated multipliers
using Very High Speed Integrated Circuit Hardware Description
Language (VHDL). The Virtex-5 FPGA shows significant
improvement as compared to Spartan-3AN FPGA device. The
Virtex-5 FPGA device shows better performance with a percentage
ratio of number of occupied slices for standard to truncated
multipliers is increased from 40% to 73.86% as compared to Spartan-
3AN is decreased from 68.75% to 58.78%. Results show that the
anomaly in Spartan-3AN FPGA device average connection and
maximum pin delay have been efficiently reduced in Virtex-5 FPGA
device.
Abstract: Multicarrier transmission system such as Orthogonal
Frequency Division Multiplexing (OFDM) is a promising technique
for high bit rate transmission in wireless communication system.
OFDM is a spectrally efficient modulation technique that can achieve
high speed data transmission over multipath fading channels without
the need for powerful equalization techniques. However the price
paid for this high spectral efficiency and less intensive equalization
is low power efficiency. OFDM signals are very sensitive to nonlinear
effects due to the high Peak-to-Average Power Ratio (PAPR),
which leads to the power inefficiency in the RF section of the
transmitter. This paper investigates the effect of PAPR reduction on
the performance parameter of multicarrier communication system.
Performance parameters considered are power consumption of Power
Amplifier (PA) and Digital-to-Analog Converter (DAC), power amplifier
efficiency, SNR of DAC and BER performance of the system.
From our analysis it is found that irrespective of PAPR reduction
technique being employed, the power consumption of PA and DAC
reduces and power amplifier efficiency increases due to reduction in
PAPR. Moreover, it has been shown that for a given BER performance
the requirement of Input-Backoff (IBO) reduces with reduction in
PAPR.
Abstract: Due to availability of powerful image processing software
and improvement of human computer knowledge, it becomes
easy to tamper images. Manipulation of digital images in different
fields like court of law and medical imaging create a serious problem
nowadays. Copy-move forgery is one of the most common types
of forgery which copies some part of the image and pastes it to
another part of the same image to cover an important scene. In
this paper, a copy-move forgery detection method proposed based
on Fourier transform to detect forgeries. Firstly, image is divided to
same size blocks and Fourier transform is performed on each block.
Similarity in the Fourier transform between different blocks provides
an indication of the copy-move operation. The experimental results
prove that the proposed method works on reasonable time and works
well for gray scale and colour images. Computational complexity
reduced by using Fourier transform in this method.
Abstract: This paper proposes and analyses the wireless
telecommunication system with multiple antennas to the emission
and reception MIMO (multiple input multiple output) with space
diversity in a OFDM context. In particular it analyses the
performance of a DTT (Digital Terrestrial Television) broadcasting
system that includes MIMO-OFDM techniques. Different
propagation channel models and configurations are considered for
each diversity scheme. This study has been carried out in the context
of development of the next generation DVB-T/H and WRAN.
Abstract: The use of new technologies such internet (e-mail, chat
rooms) and cell phones has steeply increased in recent years.
Especially among children and young people, use of technological
tools and equipments is widespread. Although many teachers and
administrators now recognize the problem of school bullying, few are
aware that students are being harassed through electronic
communication. Referred to as electronic bullying, cyber bullying, or
online social cruelty, this phenomenon includes bullying through email,
instant messaging, in a chat room, on a website, or through
digital messages or images sent to a cell phone. Cyber bullying is
defined as causing deliberate/intentional harm to others using internet
or other digital technologies. It has a quantitative research design nd
uses relational survey as its method. The participants consisted of
300 secondary school students in the city of Konya, Turkey. 195
(64.8%) participants were female and 105 (35.2%) were male. 39
(13%) students were at grade 1, 187 (62.1%) were at grade 2 and 74
(24.6%) were at grade 3. The “Cyber Bullying Question List"
developed by Ar─▒cak (2009) was given to students. Following
questions about demographics, a functional definition of cyber
bullying was provided. In order to specify students- human values,
“Human Values Scale (HVS)" developed by Dilmaç (2007) for
secondary school students was administered. The scale consists of 42
items in six dimensions. Data analysis was conducted by the primary
investigator of the study using SPSS 14.00 statistical analysis
software. Descriptive statistics were calculated for the analysis of
students- cyber bullying behaviour and simple regression analysis was
conducted in order to test whether each value in the scale could
explain cyber bullying behaviour.