Abstract: This paper will discuss how we optimize our physical
verification flow in our IC Design Department having various rule
decks from multiple foundries. Our ultimate goal is to achieve faster
time to tape-out and avoid schedule delay. Currently the physical
verification runtimes and memory usage have drastically increased
with the increasing number of design rules, design complexity, and
the size of the chips to be verified. To manage design violations, we
use a number of solutions to reduce the amount of violations needed
to be checked by physical verification engineers. The most important
functions in physical verifications are DRC (design rule check), LVS
(layout vs. schematic), and XRC (extraction). Since we have a
multiple number of foundries for our design tape-outs, we need a
flow that improve the overall turnaround time and ease of use of the
physical verification process. The demand for fast turnaround time is
even more critical since the physical design is the last stage before
sending the layout to the foundries.
Abstract: A new interface circuit for capacitive sensor is
presented. This paper presents the design and simulation of soil
moisture capacitive sensor interface circuit based on phase
differential technique. The circuit has been designed and fabricated
using MIMOS- 0.35"m CMOS technology. Simulation and test
results show linear characteristic from 36 – 52 degree phase
difference, representing 0 – 100% in soil moisture level. Test result
shows the circuit has sensitivity of 0.79mV/0.10 phase difference,
translating into resolution of 10% soil moisture level.