Game-Tree Simplification by Pattern Matching and Its Acceleration Approach using an FPGA

In this paper, we propose a Connect6 solver which adopts a hybrid approach based on a tree-search algorithm and image processing techniques. The solver must deal with the complicated computation and provide high performance in order to make real-time decisions. The proposed approach enables the solver to be implemented on a single Spartan-6 XC6SLX45 FPGA produced by XILINX without using any external devices. The compact implementation is achieved through image processing techniques to optimize a tree-search algorithm of the Connect6 game. The tree search is widely used in computer games and the optimal search brings the best move in every turn of a computer game. Thus, many tree-search algorithms such as Minimax algorithm and artificial intelligence approaches have been widely proposed in this field. However, there is one fundamental problem in this area; the computation time increases rapidly in response to the growth of the game tree. It means the larger the game tree is, the bigger the circuit size is because of their highly parallel computation characteristics. Here, this paper aims to reduce the size of a Connect6 game tree using image processing techniques and its position symmetric property. The proposed solver is composed of four computational modules: a two-dimensional checkmate strategy checker, a template matching module, a skilful-line predictor, and a next-move selector. These modules work well together in selecting next moves from some candidates and the total amount of their circuits is small. The details of the hardware design for an FPGA implementation are described and the performance of this design is also shown in this paper.

Doping of Conveyor Belt Materials with Nanostructured Fillers to Adapt Innovative Performance Characteristics

The “conveyor belt" as a product represents a complex high performance component with a wide range of different applications. Further development of these highly complex components demands an integration of new technologies and new enhanced materials. In this context nanostructured fillers appear to have a more promising effect on the performance of the conveyor belt composite than conventional micro-scaled fillers. Within the project “DotTrans" nanostructured fillers, for example silicon dioxide, are used to optimize performance parameters of conveyor belt systems. The objective of the project includes operating parameters like energy consumption or friction characteristics as well as adaptive parameters like cut or wear resistance.

Scalable Deployment and Configuration of High-Performance Virtual Clusters

Virtualization and high performance computing have been discussed from a performance perspective in recent publications. We present and discuss a flexible and efficient approach to the management of virtual clusters. A virtual machine management tool is extended to function as a fabric for cluster deployment and management. We show how features such as saving the state of a running cluster can be used to avoid disruption. We also compare our approach to the traditional methods of cluster deployment and present benchmarks which illustrate the efficiency of our approach.

Multimodal Biometric System Based on Near- Infra-Red Dorsal Hand Geometry and Fingerprints for Single and Whole Hands

Prior research evidenced that unimodal biometric systems have several tradeoffs like noisy data, intra-class variations, restricted degrees of freedom, non-universality, spoof attacks, and unacceptable error rates. In order for the biometric system to be more secure and to provide high performance accuracy, more than one form of biometrics are required. Hence, the need arise for multimodal biometrics using combinations of different biometric modalities. This paper introduces a multimodal biometric system (MMBS) based on fusion of whole dorsal hand geometry and fingerprints that acquires right and left (Rt/Lt) near-infra-red (NIR) dorsal hand geometry (HG) shape and (Rt/Lt) index and ring fingerprints (FP). Database of 100 volunteers were acquired using the designed prototype. The acquired images were found to have good quality for all features and patterns extraction to all modalities. HG features based on the hand shape anatomical landmarks were extracted. Robust and fast algorithms for FP minutia points feature extraction and matching were used. Feature vectors that belong to similar biometric traits were fused using feature fusion methodologies. Scores obtained from different biometric trait matchers were fused using the Min-Max transformation-based score fusion technique. Final normalized scores were merged using the sum of scores method to obtain a single decision about the personal identity based on multiple independent sources. High individuality of the fused traits and user acceptability of the designed system along with its experimental high performance biometric measures showed that this MMBS can be considered for med-high security levels biometric identification purposes.

Implementation of a Reed-Solomon Code as an ECC in Yet Another Flash File System

Flash memory has become an important storage device in many embedded systems because of its high performance, low power consumption and shock resistance. Multi-level cell (MLC) is developed as an effective solution for reducing the cost and increasing the storage density in recent years. However, most of flash file system cannot handle the error correction sufficiently. To correct more errors for MLC, we implement Reed-Solomon (RS) code to YAFFS, what is widely used for flash-based file system. RS code has longer computing time but the correcting ability is much higher than that of Hamming code.

An Efficient Run Time Interface for Heterogeneous Architecture of Large Scale Supercomputing System

In this paper we propose a novel Run Time Interface (RTI) technique to provide an efficient environment for MPI jobs on the heterogeneous architecture of PARAM Padma. It suggests an innovative, unified framework for the job management interface system in parallel and distributed computing. This approach employs proxy scheme. The implementation shows that the proposed RTI is highly scalable and stable. Moreover RTI provides the storage access for the MPI jobs in various operating system platforms and improve the data access performance through high performance C-DAC Parallel File System (C-PFS). The performance of the RTI is evaluated by using the standard HPC benchmark suites and the simulation results show that the proposed RTI gives good performance on large scale supercomputing system.

Optimal Design of Airfoil Platform Shapes with High Aspect Ratio Using Genetic Algorithm

Unmanned aerial vehicles (UAVs) performing their operations for a long time have been attracting much attention in military and civil aviation industries for the past decade. The applicable field of UAV is changing from the military purpose only to the civil one. Because of their low operation cost, high reliability and the necessity of various application areas, numerous development programs have been initiated around the world. To obtain the optimal solutions of the design variable (i.e., sectional airfoil profile, wing taper ratio and sweep) for high performance of UAVs, both the lift and lift-to-drag ratio are maximized whereas the pitching moment should be minimized, simultaneously. It is found that the lift force and lift-to-drag ratio are linearly dependent and a unique and dominant solution are existed. However, a trade-off phenomenon is observed between the lift-to-drag ratio and pitching moment. As the result of optimization, sixty-five (65) non-dominated Pareto individuals at the cutting edge of design spaces that are decided by airfoil shapes can be obtained.

Design and Implementation of Shared Memory based Parallel File System Logging Method for High Performance Computing

I/O workload is a critical and important factor to analyze I/O pattern and file system performance. However tracing I/O operations on the fly distributed parallel file system is non-trivial due to collection overhead and a large volume of data. In this paper, we design and implement a parallel file system logging method for high performance computing using shared memory-based multi-layer scheme. It minimizes the overhead with reduced logging operation response time and provides efficient post-processing scheme through shared memory. Separated logging server can collect sequential logs from multiple clients in a cluster through packet communication. Implementation and evaluation result shows low overhead and high scalability of this architecture for high performance parallel logging analysis.

A High Performance Technique in Harmonic Omitting Based on Predictive Current Control of a Shunt Active Power Filter

The perfect operation of common Active Filters is depended on accuracy of identification system distortion. Also, using a suitable method in current injection and reactive power compensation, leads to increased filter performance. Due to this fact, this paper presents a method based on predictive current control theory in shunt active filter applications. The harmonics of the load current is identified by using o–d–q reference frame on load current and eliminating the DC part of d–q components. Then, the rest of these components deliver to predictive current controller as a Threephase reference current by using Park inverse transformation. System is modeled in discreet time domain. The proposed method has been tested using MATLAB model for a nonlinear load (with Total Harmonic Distortion=20%). The simulation results indicate that the proposed filter leads to flowing a sinusoidal current (THD=0.15%) through the source. In addition, the results show that the filter tracks the reference current accurately.

Mechanical and Hydric Properties of High- Performance Concrete Containing Natural Zeolites

Mechanical and water transport properties of high performance concrete (HPC) containing natural zeolite as partial replacement of Portland cement are studied. Experimental results show that in the investigated mixes the use of natural zeolite leads to an increase of porosity, decrease of compressive strength and increase of moisture diffusivity and water vapor diffusion coefficient, as compared with the reference HPC. However, for the replacement level up to 20% of the mass of Portland cement the concretes still maintain their high performance character and exhibit acceptable water transport properties. Therefore, natural zeolite can be considered an environmental friendly binder with a potential to replace a part of Portland cement in concrete in building industry.

High Performance Liquid Chromatographic Method for Determination of Colistin Sulfate and its Application in Medicated Premixand Animal Feed

The aim of the present study was to develop and validate an inexpensive and simple high performance liquid chromatographic (HPLC) method for the determination of colistin sulfate. Separation of colistin sulfate was achieved on a ZORBAX Eclipse XDB-C18 column using UV detection at λ=215 nm. The mobile phase was 30 mM sulfate buffer (pH 2.5):acetonitrile(76:24). An excellent linearity (r2=0.998) was found in the concentration range of 25 - 400 μg/mL. Intra- day and inter-day precisions of method (%RSD, n=3) were less than 7.9%.The developed and validated method was applied to determination of the content of colistin sulfate in medicated premix and animal feed sample.The recovery of colistin from animal feed was satisfactorily ranged from 90.92 to 93.77%. The results demonstrated that the HPLC method developed in this work is appropriate for direct determination of colistin sulfate in commercial medicated premixes and animal feed.

Implementing High Performance VPN Router using Cavium-s CN2560 Security Processor

IPsec protocol[1] is a set of security extensions developed by the IETF and it provides privacy and authentication services at the IP layer by using modern cryptography. In this paper, we describe both of H/W and S/W architectures of our router system, SRS-10. The system is designed to support high performance routing and IPsec VPN. Especially, we used Cavium-s CN2560 processor to implement IPsec processing in inline-mode.

IPSO Based UPFC Robust Output Feedback Controllers for Damping of Low Frequency Oscillations

On the basis of the linearized Phillips-Herffron model of a single-machine power system, a novel method for designing unified power flow controller (UPFC) based output feedback controller is presented. The design problem of output feedback controller for UPFC is formulated as an optimization problem according to with the time domain-based objective function which is solved by iteration particle swarm optimization (IPSO) that has a strong ability to find the most optimistic results. To ensure the robustness of the proposed damping controller, the design process takes into account a wide range of operating conditions and system configurations. The simulation results prove the effectiveness and robustness of the proposed method in terms of a high performance power system. The simulation study shows that the designed controller by Iteration PSO performs better than Classical PSO in finding the solution.

Minimizing the Broadcast Traffic in the Jordanian Discovery Schools Network using PPPoE

Discovery schools in Jordan are connected in one flat ATM bridge network. All Schools connected to the network will hear broadcast traffic. High percentage of unwanted traffic such as broadcast, consumes the bandwidth between schools and QRC. Routers in QRC have high CPU utilization. The number of connections on the router is very high, and may exceed recommend manufacturing specifications. One way to minimize number of connections to the routers in QRC, and minimize broadcast traffic is to use PPPoE. In this study, a PPPoE solution has been presented which shows high performance for the clients when accessing the school server resources. Despite the large number of the discovery schools at MoE, the experimental results show that the PPPoE solution is able to yield a satisfactory performance for each client at the school and noticeably reduce the traffic broadcast to the QRC.

Development of a Novel Low-Cost Flight Simulator for Pilot Training

A novel low-cost flight simulator with the development goals cost effectiveness and high performance has been realized for meeting the huge pilot training needs of airlines. The simulator consists of an aircraft dynamics model, a sophisticated designed low-profile electrical driven motion system with a subsided cabin, a mixed reality based semi-virtual cockpit system, a control loading system and some other subsystems. It shows its advantages over traditional flight simulator by its features achieved with open architecture, software solutions and low-cost hardware.

Specification of Attributes of a Multimedia Presentation for Presentation Manager

A multimedia presentation system refers to the integration of a multimedia database with a presentation manager which has the functionality of content selection, organization and playout of multimedia presentations. It requires high performance of involved system components. Starting from multimedia information capture until the presentation delivery, high performance tools are required for accessing, manipulating, storing and retrieving these segments, for transferring and delivering them in a presentation terminal according to a playout order. The organization of presentations is a complex task in that the display order of presentation contents (in time and space) must be specified. A multimedia presentation contains audio, video, images and text media types. The critical decisions for presentation construction include what the contents are, how the contents are organized, and once the decision is made on the organization of the contents of the presentation, it must be conveyed to the end user in the correct organizational order and in a timely fashion. This paper introduces a framework for specification of multimedia presentations and describes the design of sample presentations using this framework from a multimedia database.

Using the PGAS Programming Paradigm for Biological Sequence Alignment on a Chip Multi-Threading Architecture

The Partitioned Global Address Space (PGAS) programming paradigm offers ease-of-use in expressing parallelism through a global shared address space while emphasizing performance by providing locality awareness through the partitioning of this address space. Therefore, the interest in PGAS programming languages is growing and many new languages have emerged and are becoming ubiquitously available on nearly all modern parallel architectures. Recently, new parallel machines with multiple cores are designed for targeting high performance applications. Most of the efforts have gone into benchmarking but there are a few examples of real high performance applications running on multicore machines. In this paper, we present and evaluate a parallelization technique for implementing a local DNA sequence alignment algorithm using a PGAS based language, UPC (Unified Parallel C) on a chip multithreading architecture, the UltraSPARC T1.

Enhancement of Shape Description and Representation by Slope

Representation and description of object shapes by the slopes of their contours or borders are proposed. The idea is to capture the essence of the features that make it easier for a shape to be stored, transmitted, compared and recognized. These features must be independent of translation, rotation and scaling of the shape. A approach is proposed to obtain high performance, efficiency and to merge the boundaries into sequence of straight line segments with the fewest possible segments. Evaluation on the performance of the proposed method is based on its comparison with established method of object shape description.

A Novel Low Power Very Low Voltage High Performance Current Mirror

In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.