Abstract: In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.
Abstract: MRAM technology provides a combination of fast
access time, non-volatility, data retention and endurance. While a
growing interest is given to two-terminal Magnetic Tunnel Junctions
(MTJ) based on Spin-Transfer Torque (STT) switching as the
potential candidate for a universal memory, its reliability is
dramatically decreased because of the common writing/reading path.
Three-terminal MTJ based on Spin-Orbit Torque (SOT) approach
revitalizes the hope of an ideal MRAM. It can overcome the
reliability barrier encountered in current two-terminal MTJs by
separating the reading and the writing path. In this paper, we study
two possible writing schemes for the SOT-MTJ device based on
recently fabricated samples. While the first is based on precessional
switching, the second requires the presence of permanent magnetic
field. Based on an accurate Verilog-A model, we simulate the two
writing techniques and we highlight advantages and drawbacks of
each one. Using the second technique, pioneering logic circuits based
on the three-terminal architecture of the SOT-MTJ described in this
work are under development with preliminary attractive results.