Abstract: A novel design technique employing CMOS Current
Feedback Operational Amplifier (CFOA) is presented. The feature of
consumption very low power in designing pseudo-OTA is used to
decreasing the total power consumption of the proposed CFOA. This
design approach applies pseudo-OTA as input stage cascaded with
buffer stage. Moreover, the DC input offset voltage and harmonic
distortion (HD) of the proposed CFOA are very low values compared
with the conventional CMOS CFOA due to the symmetrical input
stage. P-Spice simulation results are obtained using 0.18μm MIETEC
CMOS process parameters and supply voltage of ±1.2V, 50μA
biasing current. The p-spice simulation shows excellent improvement
of the proposed CFOA over existing CMOS CFOA. Some of these
performance parameters, for example, are DC gain of 62. dB, openloop
gain bandwidth product of 108 MHz, slew rate (SR+) of
+71.2V/μS, THD of -63dB and DC consumption power (PC) of
2mW.
Abstract: In the literature, Improved Recycling Folded Cascode (IRFC) Operational Transconductance Amplifier (OTA) is proposed for enhancing the DC gain and the Unity Gain Bandwidth (UGB) of the Recycling Folded Cascode (RFC) OTA. In this paper, an enhanced IRFC (EIRFC) OTA which uses positive feedback at the cascode node is proposed for enhancing the differential mode (DM) gain without changing the unity gain bandwidth (UGB) and lowering the Common mode (CM) gain. For the purpose of comparison, IRFC and EIRFC OTAs are implemented using UMC 90nm CMOS technology and studied through simulation. From the simulation, it is found that the DM gain and CM gain of EIRFC OTA is higher by 6dB and lower by 38dB respectively, compared to that of IRFC OTA for the same power and area. The slew rate of EIRFC OTA is also higher by a factor of 1.5.
Abstract: A fast settling multipath CMOS OTA for high speed
switched capacitor applications is presented here. With the basic
topology similar to folded-cascode, bandwidth and DC gain of the
OTA are enhanced by adding extra paths for signal from input to
output. Designed circuit is simulated with HSPICE using level 49
parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC
gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained
is 1.15GHz. These results confirm that adding extra paths for signal
can improve DC gain and UGB of folded-cascode significantly.
Abstract: In recent years Operational Transconductance Amplifier based high frequency integrated circuits, filters and systems have been widely investigated. The usefulness of OTAs over conventional OP-Amps in the design of both first order and second order active filters are well documented. This paper discusses some of the tunability issues using the Matlab/Simulink® software which are previously unreported for any commercial OTA. Using the simulation results two first order voltage controlled all pass filters with phase tuning capability are proposed.
Abstract: This paper presents an optimized methodology to
folded cascode operational transconductance amplifier (OTA) design.
The design is done in different regions of operation, weak inversion,
strong inversion and moderate inversion using the gm/ID methodology
in order to optimize MOS transistor sizing.
Using 0.35μm CMOS process, the designed folded cascode OTA
achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz
in strong inversion mode. In moderate inversion mode, it has a 92dB
DC gain and provides a gain bandwidth product of around 69MHz.
The OTA circuit has a DC gain of 75.5dB and unity-gain frequency
limited to 19.14MHZ in weak inversion region.