Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology
This paper presents an optimized methodology to
folded cascode operational transconductance amplifier (OTA) design.
The design is done in different regions of operation, weak inversion,
strong inversion and moderate inversion using the gm/ID methodology
in order to optimize MOS transistor sizing.
Using 0.35μm CMOS process, the designed folded cascode OTA
achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz
in strong inversion mode. In moderate inversion mode, it has a 92dB
DC gain and provides a gain bandwidth product of around 69MHz.
The OTA circuit has a DC gain of 75.5dB and unity-gain frequency
limited to 19.14MHZ in weak inversion region.
[1] M.G.R. Degrauwe et al.., "IDAC: An interactive design tool for analog
CMOS circuits," IEEE J.Solid-State circuits, vol. sc-22, no. 6,
dec.(1987), pp. 1106-1116.
[2] R.Harjani, R.A. Rutenbar and L.R. Carley, "OASYS: A framework for
analog circuit synthesis," IEEE Trans. Computer-Aided Design, vol. 8,
no. 12, Dec. (1989), pp. 1247-1266.
[3] H. Y. Koh, C.H Séquin and P.R. Gray, "OPASYN: A compiler for
CMOS operational amplifiers," IEEE Trans. Computer-Aided Design,
vol. 8, no. 12, Dec. (1990), pp. 113-125.
[4] J.P. Harvey, M.I. Elmasry and B. Leung, "STAIC: An interactive
framework for synthesizing CMOS band BiCMOS analog circuits,"
IEEE Trans.Computer-Aided Design, vol. 11, no. 11, Nov. (1992), pp.
1402-1417.
[5] M. Fakhfakh, M. Loulou, and N. Masmoudi, "Optimizing performances
of switched current memory cells through a heuristic," Journal of
Analog Integrated Circuits and Signal Processing, Springer Editor,
(2006).
[6] R.K. Brayton, G.D. Hachtel and A.L. Sangiovanni-Vincentelli, "A
survey of optimization techniques for integrated-circuit design," Proc.
IEEE, vol. 69, no. 10, Oct. 1981, pp. 1334-1364.
[7] W. Nye et al.., "DELIGHT.SPICE: An optimization-based system for
the design of integrated circuits,"IEEE Trans.Computer-Aided Design,
vol. 7, no. 4, Apr. (1988), pp. 501-519.
[8] S.W. Director and G.D. Hachtel, "The simplicial approximation
approach to design centering,"IEEE Trans. Circuits Syst. I, vol. Cas-29,
no. 2, Feb. (1982),pp. 88-96
[9] K.J.Antreich and R.K Koblitz, "Design centering by yield prediction,"
IEEE Trans. Circuits Syst. I, vol. Cas-29, no. 2, Feb. (1982), pp. 88-96.
[10] P. Feldmannand S. W. Director," Integrated circuit quality optimization
using surface integrals ," IEEE Trans. Computer-Aided Design vol. 12,
no. 12,Dec. 1993; pp. (1868-1879).
[11] K.J.Antreich, H.E. Hraeb and C.U. Wieser," Circuit analysis and
optimization driven by worst-case distances," IEEE Trans. Computer-
Aided Design vol. 13, no. 1, Jan. (1994), pp. 57-71.
[12] A. Dharchoudhury and S.M. Kang, "Worst-case analysis and
optimization of VLSI circuit performances," IEEE Trans. Computer-
Aided Design vol. 14, no. 4,Apr. (1995), pp. 481-492.
[13] A. Burmen et al.., "Automated robust design and optimization of
integrated circuits by means of penalty functions," int. J. Electron.
Comm.,57, no. 1, (2003), pp. 47-56.
[14] M. del Mar Hershenson, S.P. Boyd and T.H. Lee, "GPCAD: A tool for
CMOS op-amp synthesis," 1998 IEEE/ACM Int. Conf.Comput-Aided
Design, New York, (1998), pp. 296-303.
[15] M. del Mar Hershenson, S.P. Boyd and T.H. Lee, "Optimal design of a
CMOS op-amp via geometric programming," IEEE Trans. Computer-
Aided Design vol. 20, no. 1, Jan. (2001), pp. 1-21.
[16] G. Gielen at al..,"An analogue module generator for mixed
analogue/digital ASIC design," Int. J.Circuit theory and App.,vol. 23,
no. 4, July-Aug. (1995),pp.269-283.
[17] G.G.E. Gielen, H.C.C. Walscharts and W.M.C. Sansen," Analog circuit
design optimization based on symbolic simulation and simulated
annealing," IEEE J. Solid-State circuits, vol. 25, no. 3 June (1990), pp.
707-713.
[18] E.S.Ochotta, R.A. Rutenbar and L.R. Carley, "Sunthesis of highperformances
analog circuits in ASTRX/OBLX,"IEEE Trans.
Computer-Aided Design vol. 15, no. 3, Mar. (1996), pp. 273-294.
[19] G. Debyser and G. Gielen, "Efficient analog circuit synthesis with
simultaneous yield and robustness optimization," 1998 IEEE/ACM, Int.
Conf. Computer-Aided Design, New York, (1998), pp. 308-311.
[20] R. Schwencker et al.., "Automating the sizing of analog CMOS circuits
by consideration of structural constraints," DATE Conf. And
Exhibition, 1999, Los Alamitos, (1999), pp. 323-327.
[21] R. Phelps et al., "Anaconda: simulation-based synthesis of analog
circuitsvia stochastic pattern search," IEEE Trans. Computer-Aided
Design vol. 19, no. 6, June (2000), pp. 703-717.
[22] T. Mukherjee, L.R. Carley and R.A Rutenbar, "Efficient handling of
operating range and manufacturing line variations in analog cell
synthesis," IEEE Trans. Computer-Aided Design vol. 19, no. 8, Aug.
(2000), pp. 825-839.
[23] F. Schenkel et al., "Mismatch analysis and direct yield optimization by
spec-wise linearization and feasibility-guided search," Proc. 38th DAC,
New York, (2001), pp. 22-38.
[24] P. Mandal and V. Visvanthan, "CMOS op-amp sizing using a geometric
programming formulation," IEEE Trans. Computer-Aided Design vol.
20, no. 1, Jan. (2001), pp. 22-38.
[25] Behzad Razavi, "Design of Analog CMOS Integrated Circuit",
TheMcGraw-Hill Companies, Inc., United States, (2001), ISBN:0-07-
118815-0.
[26] M. Loulou, S. Ait Ali and N. Masmoudi, "Conception et Optimisation
d-un Amplificateur Opérationnel Rail to Rail CMOS Faible Tension
Faible Consommation" Journal Scientifique Libannais, le Conseil
National de la Recherche Scientifique- Liban Vol. 4, N┬░.1, (2003), pp.
75-90.
[27] Silveira, D. Flandre et P.G.A. Jespers, "A gm/ID based methodology
for the design of CMOS analog circuits and application to the synthesis
of a SOI micropower OTA", IEEE J. of Solid State Circuits, vol. 31, n.
9, sept. (1996).
[28] M. Banu, J. M. Khoury, and Y. Tsividis, "Fully Differential Operational
Amplifier with Accurate Output Balancing," IEEE Journal of Solid
State circuits, Vol. 23, No. 6, pp. December (1990).
[29] Y. Libin, M. Steyaert, and W. Sansen, "A 1-V 140-╬╝W 88-dB Audio
Sigma-Delta Modulator in 90-nm CMOS", IEEE Journal of Solid State
circuit, Vol. 39, NO. 11, November (2004).
[30] Craig Brendan Keogh, "Low-Power Multi-Bit ΣΔ-Modulator Design
for portable Audio Application", Stockholm, March (2005).
[1] M.G.R. Degrauwe et al.., "IDAC: An interactive design tool for analog
CMOS circuits," IEEE J.Solid-State circuits, vol. sc-22, no. 6,
dec.(1987), pp. 1106-1116.
[2] R.Harjani, R.A. Rutenbar and L.R. Carley, "OASYS: A framework for
analog circuit synthesis," IEEE Trans. Computer-Aided Design, vol. 8,
no. 12, Dec. (1989), pp. 1247-1266.
[3] H. Y. Koh, C.H Séquin and P.R. Gray, "OPASYN: A compiler for
CMOS operational amplifiers," IEEE Trans. Computer-Aided Design,
vol. 8, no. 12, Dec. (1990), pp. 113-125.
[4] J.P. Harvey, M.I. Elmasry and B. Leung, "STAIC: An interactive
framework for synthesizing CMOS band BiCMOS analog circuits,"
IEEE Trans.Computer-Aided Design, vol. 11, no. 11, Nov. (1992), pp.
1402-1417.
[5] M. Fakhfakh, M. Loulou, and N. Masmoudi, "Optimizing performances
of switched current memory cells through a heuristic," Journal of
Analog Integrated Circuits and Signal Processing, Springer Editor,
(2006).
[6] R.K. Brayton, G.D. Hachtel and A.L. Sangiovanni-Vincentelli, "A
survey of optimization techniques for integrated-circuit design," Proc.
IEEE, vol. 69, no. 10, Oct. 1981, pp. 1334-1364.
[7] W. Nye et al.., "DELIGHT.SPICE: An optimization-based system for
the design of integrated circuits,"IEEE Trans.Computer-Aided Design,
vol. 7, no. 4, Apr. (1988), pp. 501-519.
[8] S.W. Director and G.D. Hachtel, "The simplicial approximation
approach to design centering,"IEEE Trans. Circuits Syst. I, vol. Cas-29,
no. 2, Feb. (1982),pp. 88-96
[9] K.J.Antreich and R.K Koblitz, "Design centering by yield prediction,"
IEEE Trans. Circuits Syst. I, vol. Cas-29, no. 2, Feb. (1982), pp. 88-96.
[10] P. Feldmannand S. W. Director," Integrated circuit quality optimization
using surface integrals ," IEEE Trans. Computer-Aided Design vol. 12,
no. 12,Dec. 1993; pp. (1868-1879).
[11] K.J.Antreich, H.E. Hraeb and C.U. Wieser," Circuit analysis and
optimization driven by worst-case distances," IEEE Trans. Computer-
Aided Design vol. 13, no. 1, Jan. (1994), pp. 57-71.
[12] A. Dharchoudhury and S.M. Kang, "Worst-case analysis and
optimization of VLSI circuit performances," IEEE Trans. Computer-
Aided Design vol. 14, no. 4,Apr. (1995), pp. 481-492.
[13] A. Burmen et al.., "Automated robust design and optimization of
integrated circuits by means of penalty functions," int. J. Electron.
Comm.,57, no. 1, (2003), pp. 47-56.
[14] M. del Mar Hershenson, S.P. Boyd and T.H. Lee, "GPCAD: A tool for
CMOS op-amp synthesis," 1998 IEEE/ACM Int. Conf.Comput-Aided
Design, New York, (1998), pp. 296-303.
[15] M. del Mar Hershenson, S.P. Boyd and T.H. Lee, "Optimal design of a
CMOS op-amp via geometric programming," IEEE Trans. Computer-
Aided Design vol. 20, no. 1, Jan. (2001), pp. 1-21.
[16] G. Gielen at al..,"An analogue module generator for mixed
analogue/digital ASIC design," Int. J.Circuit theory and App.,vol. 23,
no. 4, July-Aug. (1995),pp.269-283.
[17] G.G.E. Gielen, H.C.C. Walscharts and W.M.C. Sansen," Analog circuit
design optimization based on symbolic simulation and simulated
annealing," IEEE J. Solid-State circuits, vol. 25, no. 3 June (1990), pp.
707-713.
[18] E.S.Ochotta, R.A. Rutenbar and L.R. Carley, "Sunthesis of highperformances
analog circuits in ASTRX/OBLX,"IEEE Trans.
Computer-Aided Design vol. 15, no. 3, Mar. (1996), pp. 273-294.
[19] G. Debyser and G. Gielen, "Efficient analog circuit synthesis with
simultaneous yield and robustness optimization," 1998 IEEE/ACM, Int.
Conf. Computer-Aided Design, New York, (1998), pp. 308-311.
[20] R. Schwencker et al.., "Automating the sizing of analog CMOS circuits
by consideration of structural constraints," DATE Conf. And
Exhibition, 1999, Los Alamitos, (1999), pp. 323-327.
[21] R. Phelps et al., "Anaconda: simulation-based synthesis of analog
circuitsvia stochastic pattern search," IEEE Trans. Computer-Aided
Design vol. 19, no. 6, June (2000), pp. 703-717.
[22] T. Mukherjee, L.R. Carley and R.A Rutenbar, "Efficient handling of
operating range and manufacturing line variations in analog cell
synthesis," IEEE Trans. Computer-Aided Design vol. 19, no. 8, Aug.
(2000), pp. 825-839.
[23] F. Schenkel et al., "Mismatch analysis and direct yield optimization by
spec-wise linearization and feasibility-guided search," Proc. 38th DAC,
New York, (2001), pp. 22-38.
[24] P. Mandal and V. Visvanthan, "CMOS op-amp sizing using a geometric
programming formulation," IEEE Trans. Computer-Aided Design vol.
20, no. 1, Jan. (2001), pp. 22-38.
[25] Behzad Razavi, "Design of Analog CMOS Integrated Circuit",
TheMcGraw-Hill Companies, Inc., United States, (2001), ISBN:0-07-
118815-0.
[26] M. Loulou, S. Ait Ali and N. Masmoudi, "Conception et Optimisation
d-un Amplificateur Opérationnel Rail to Rail CMOS Faible Tension
Faible Consommation" Journal Scientifique Libannais, le Conseil
National de la Recherche Scientifique- Liban Vol. 4, N┬░.1, (2003), pp.
75-90.
[27] Silveira, D. Flandre et P.G.A. Jespers, "A gm/ID based methodology
for the design of CMOS analog circuits and application to the synthesis
of a SOI micropower OTA", IEEE J. of Solid State Circuits, vol. 31, n.
9, sept. (1996).
[28] M. Banu, J. M. Khoury, and Y. Tsividis, "Fully Differential Operational
Amplifier with Accurate Output Balancing," IEEE Journal of Solid
State circuits, Vol. 23, No. 6, pp. December (1990).
[29] Y. Libin, M. Steyaert, and W. Sansen, "A 1-V 140-╬╝W 88-dB Audio
Sigma-Delta Modulator in 90-nm CMOS", IEEE Journal of Solid State
circuit, Vol. 39, NO. 11, November (2004).
[30] Craig Brendan Keogh, "Low-Power Multi-Bit ΣΔ-Modulator Design
for portable Audio Application", Stockholm, March (2005).
@article{"International Journal of Electrical, Electronic and Communication Sciences:56113", author = "H. Daoud Dammak and S. Bensalem and S. Zouari and M. Loulou", title = "Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology", abstract = "This paper presents an optimized methodology to
folded cascode operational transconductance amplifier (OTA) design.
The design is done in different regions of operation, weak inversion,
strong inversion and moderate inversion using the gm/ID methodology
in order to optimize MOS transistor sizing.
Using 0.35μm CMOS process, the designed folded cascode OTA
achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz
in strong inversion mode. In moderate inversion mode, it has a 92dB
DC gain and provides a gain bandwidth product of around 69MHz.
The OTA circuit has a DC gain of 75.5dB and unity-gain frequency
limited to 19.14MHZ in weak inversion region.", keywords = "CMOS IC design, Folded Cascode OTA, gm/ID
methodology, optimization.", volume = "2", number = "9", pages = "1930-6", }
