Abstract: In this paper, a neural network tuned fuzzy controller
is proposed for controlling Multi-Input Multi-Output (MIMO)
systems. For the convenience of analysis, the structure of MIMO
fuzzy controller is divided into single input single-output (SISO)
controllers for controlling each degree of freedom. Secondly,
according to the characteristics of the system-s dynamics coupling, an
appropriate coupling fuzzy controller is incorporated to improve the
performance. The simulation analysis on a two-level mass–spring
MIMO vibration system is carried out and results show the
effectiveness of the proposed fuzzy controller. The performance
though improved, the computational time and memory used is
comparatively higher, because it has four fuzzy reasoning blocks and
number may increase in case of other MIMO system. Then a fuzzy
neural network is designed from a set of input-output training data to
reduce the computing burden during implementation. This control
strategy can not only simplify the implementation problem of fuzzy
control, but also reduce computational time and consume less
memory.
Abstract: To increase reliability of face recognition system, the
system must be able to distinguish real face from a copy of face such
as a photograph. In this paper, we propose a fast and memory efficient
method of live face detection for embedded face recognition system,
based on the analysis of the movement of the eyes. We detect eyes in
sequential input images and calculate variation of each eye region to
determine whether the input face is a real face or not. Experimental
results show that the proposed approach is competitive and promising
for live face detection.
Abstract: The most widely used semiconductor memory types
are the Dynamic Random Access Memory (DRAM) and Static
Random Access memory (SRAM). Competition among memory
manufacturers drives the need to decrease power consumption and
reduce the probability of read failure. A technology that is relatively
new and has not been explored is the FinFET technology. In this
paper, a single cell Schmitt Trigger Based Static RAM using FinFET
technology is proposed and analyzed. The accuracy of the result is
validated by means of HSPICE simulations with 32nm FinFET
technology and the results are then compared with 6T SRAM using
the same technology.
Abstract: The batch nature limits the standard kernel principal component analysis (KPCA) methods in numerous applications, especially for dynamic or large-scale data. In this paper, an efficient adaptive approach is presented for online extraction of the kernel principal components (KPC). The contribution of this paper may be divided into two parts. First, kernel covariance matrix is correctly updated to adapt to the changing characteristics of data. Second, KPC are recursively formulated to overcome the batch nature of standard KPCA.This formulation is derived from the recursive eigen-decomposition of kernel covariance matrix and indicates the KPC variation caused by the new data. The proposed method not only alleviates sub-optimality of the KPCA method for non-stationary data, but also maintains constant update speed and memory usage as the data-size increases. Experiments for simulation data and real applications demonstrate that our approach yields improvements in terms of both computational speed and approximation accuracy.
Abstract: This paper presents a new configurable decimation
filter for sigma-delta modulators. The filter employs the Pascal-s
triangle-s theorem for building the coefficients of non-recursive
decimation filters. The filter can be connected to the back-end of
various modulators with different output accuracy. In this work two
methods are shown and then compared from area occupation
viewpoint. First method uses the memory and the second one
employs Pascal-s triangle-s method, aiming to reduce required gates.
XILINX ISE v10 is used for implementation and confirmation the
filter.
Abstract: A series of Ti based shape memory alloys with
composition of Ti50Ni49Cr1, Ti50Ni47Cr3 and Ti50Ni45Cr5 were
developed by vacuum arc-melting under a purified argon atmosphere.
The histometric and corrosion evaluation of Ti-Ni-Cr shape memory
alloys have been considered in this research work. The alloys were
developed by vacuum arc melting and implanted subcutaneously in
rabbits for 4, 8 and 12 weeks. Metallic implants were embedded in
order to determine the outcome of implantation on histometric and
corrosion evaluation of Ti-Ni-Cr metallic strips. Encapsulating
membrane formation around the alloys was minimal in the case of all
materials. After histomorphometric analyses it was possible to
demonstrate that there were no statistically significant differences
between the materials. Corrosion rate was also determined in this
study which is within acceptable range. The results showed the Ti-
Ni-Cr alloy was neither cytotoxic, nor have any systemic reaction on
living system in any of the test performed. Implantation shows good
compatibility and a potential of being used directly in vivo system.
Abstract: In-core memory requirement is a bottleneck in solving
large three dimensional Navier-Stokes finite element problem
formulations using sparse direct solvers. Out-of-core solution
strategy is a viable alternative to reduce the in-core memory
requirements while solving large scale problems. This study
evaluates the performance of various out-of-core sequential solvers
based on multifrontal or supernodal techniques in the context of
finite element formulations for three dimensional problems on a
Windows platform. Here three different solvers, HSL_MA78,
MUMPS and PARDISO are compared. The performance of these
solvers is evaluated on a 64-bit machine with 16GB RAM for finite
element formulation of flow through a rectangular channel. It is
observed that using out-of-core PARDISO solver, relatively large
problems can be solved. The implementation of Newton and
modified Newton's iteration is also discussed.
Abstract: A model predictive controller based on recursive learning is proposed. In this SISO adaptive controller, a model is automatically updated using simple recursive equations. The identified models are then stored in the memory to be re-used in the future. The decision for model update is taken based on a new control performance index. The new controller allows the use of simple linear model predictive controllers in the control of nonlinear time varying processes.
Abstract: A new conceptual architecture for low-level neural
pattern recognition is presented. The key ideas are that the brain
implements support vector machines and that support vectors are
represented as memory patterns in competitive queuing memories. A
binary classifier is built from two competitive queuing memories
holding positive and negative valence training examples respectively.
The support vector machine classification function is calculated in
synchronized evaluation cycles. The kernel is computed by bisymmetric
feed-forward networks feed by sensory input and by
competitive queuing memories traversing the complete sequence of
support vectors. Temporary summation generates the output
classification. It is speculated that perception apparatus in the brain
reuses structures that have evolved for enabling fluent execution of
prepared action sequences so that pattern recognition is built on
internalized motor programmes.
Abstract: Generally speaking, the mobile robot is capable of
sensing its surrounding environment, interpreting the sensed
information to obtain the knowledge of its location and the
environment, planning a real-time trajectory to reach the object. In
this process, the issue of obstacle avoidance is a fundamental topic to
be challenged. Thus, an adaptive path-planning control scheme is
designed without detailed environmental information, large memory
size and heavy computation burden in this study for the obstacle
avoidance of a mobile robot. In this scheme, the robot can gradually
approach its object according to the motion tracking mode, obstacle
avoidance mode, self-rotation mode, and robot state selection. The
effectiveness of the proposed adaptive path-planning control scheme
is verified by numerical simulations of a differential-driving mobile
robot under the possible occurrence of obstacle shapes.
Abstract: An efficient parallel form in digital signal processor can improve the algorithm performance. The butterfly structure is an important role in fast Fourier transform (FFT), because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which call as novel memory reference reduction methods (NMRRM) for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. In this paper, we propose a parallel-computing approach for FFT implementation on digital signal processor (DSP) which is based on data-independent property and still hold the property of low-memory reference. The proposed method combines final two steps in NMRRM FFT to perform a novel data-independent structure, besides it is very suitable for multi-operation-unit digital signal processor and dual-core system. We have applied the proposed method of radix-2 FFT algorithm in low memory reference on TI TMSC320C64x DSP. Experimental results show the method can reduce 33.8% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property.
Abstract: In the paper we submit the non-local modification of
kinetic Smoluchowski equation for binary aggregation applying to
dispersed media having memory. Our supposition consists in that that
intensity of evolution of clusters is supposed to be a function of the
product of concentrations of the lowest orders clusters at different
moments. The new form of kinetic equation for aggregation is
derived on the base of the transfer kernels approach. This approach
allows considering the influence of relaxation times hierarchy on
kinetics of aggregation process in media with memory.
Abstract: In this paper, a novel associative memory model will be proposed and applied to memory retrievals based on the conventional continuous time model. The conventional model presents memory capacity is very low and retrieval process easily converges to an equilibrium state which is very different from the stored patterns. Genetic Algorithms is well-known with the capability of global optimal search escaping local optimum on progress to reach a global optimum. Based on the well-known idea of Genetic Algorithms, this work proposes a heuristic rule to make a mutation when the state of the network is trapped in a spurious memory. The proposal heuristic associative memory show the stored capacity does not depend on the number of stored patterns and the retrieval ability is up to ~ 1.
Abstract: Hypernetworks are a generalized graph structure
representing higher-order interactions between variables. We present a
method for self-organizing hypernetworks to learn an associative
memory of sentences and to recall the sentences from this memory.
This learning method is inspired by the “mental chemistry" model of
cognition and the “molecular self-assembly" technology in
biochemistry. Simulation experiments are performed on a corpus of
natural-language dialogues of approximately 300K sentences
collected from TV drama captions. We report on the sentence
completion performance as a function of the order of word-interaction
and the size of the learning corpus, and discuss the plausibility of this
architecture as a cognitive model of language learning and memory.
Abstract: With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.
Abstract: Direction of Arrival estimation refers to defining a mathematical function called a pseudospectrum that gives an indication of the angle a signal is impinging on the antenna array. This estimation is an efficient method of improving the quality of service in a communication system by focusing the reception and transmission only in the estimated direction thereby increasing fidelity with a provision to suppress interferers. This improvement is largely dependent on the performance of the algorithm employed in the estimation. Many DOA algorithms exists amongst which are MUSIC, Root-MUSIC and ESPRIT. In this paper, performance of these three algorithms is analyzed in terms of complexity, accuracy as assessed and characterized by the CRLB and memory requirements in various environments and array sizes. It is found that the three algorithms are high resolution and dependent on the operating environment and the array size.
Abstract: Embedded systems need to respect stringent real
time constraints. Various hardware components included in such
systems such as cache memories exhibit variability and therefore
affect execution time. Indeed, a cache memory access from an
embedded microprocessor might result in a cache hit where the
data is available or a cache miss and the data need to be fetched
with an additional delay from an external memory. It is therefore
highly desirable to predict future memory accesses during
execution in order to appropriately prefetch data without incurring
delays. In this paper, we evaluate the potential of several artificial
neural networks for the prediction of instruction memory
addresses. Neural network have the potential to tackle the nonlinear
behavior observed in memory accesses during program
execution and their demonstrated numerous hardware
implementation emphasize this choice over traditional forecasting
techniques for their inclusion in embedded systems. However,
embedded applications execute millions of instructions and
therefore millions of addresses to be predicted. This very
challenging problem of neural network based prediction of large
time series is approached in this paper by evaluating various neural
network architectures based on the recurrent neural network
paradigm with pre-processing based on the Self Organizing Map
(SOM) classification technique.
Abstract: Falling has been one of the major concerns and threats
to the independence of the elderly in their daily lives. With the
worldwide significant growth of the aging population, it is essential
to have a promising solution of fall detection which is able to operate
at high accuracy in real-time and supports large scale implementation
using multiple cameras. Field Programmable Gate Array (FPGA) is a
highly promising tool to be used as a hardware accelerator in many
emerging embedded vision based system. Thus, it is the main
objective of this paper to present an FPGA-based solution of visual
based fall detection to meet stringent real-time requirements with
high accuracy. The hardware architecture of visual based fall
detection which utilizes the pixel locality to reduce memory accesses
is proposed. By exploiting the parallel and pipeline architecture of
FPGA, our hardware implementation of visual based fall detection
using FGPA is able to achieve a performance of 60fps for a series of
video analytical functions at VGA resolutions (640x480). The results
of this work show that FPGA has great potentials and impacts in
enabling large scale vision system in the future healthcare industry
due to its flexibility and scalability.
Abstract: This paper discusses the applicability of the Data
Distribution Service (DDS) for the development of automated and modular manufacturing systems which require a flexible and robust
communication infrastructure. DDS is an emergent standard for datacentric publish/subscribe middleware systems that provides an
infrastructure for platform-independent many-to-many
communication. It particularly addresses the needs of real-time systems that require deterministic data transfer, have low memory
footprints and high robustness requirements. After an overview of the
standard, several aspects of DDS are related to current challenges for the development of modern manufacturing systems with distributed architectures. Finally, an example application is presented based on a modular active fixturing system to illustrate the described aspects.
Abstract: Most scientific programs have large input and output
data sets that require out-of-core programming or use virtual memory
management (VMM). Out-of-core programming is very error-prone
and tedious; as a result, it is generally avoided. However, in many
instance, VMM is not an effective approach because it often results
in substantial performance reduction. In contrast, compiler driven I/O
management will allow a program-s data sets to be retrieved in parts,
called blocks or tiles. Comanche (COmpiler MANaged caCHE) is a
compiler combined with a user level runtime system that can be used
to replace standard VMM for out-of-core programs. We describe
Comanche and demonstrate on a number of representative problems
that it substantially out-performs VMM. Significantly our system
does not require any special services from the operating system and
does not require modification of the operating system kernel.