Abstract: This paper presents an efficient VLSI architecture
design to achieve real time video processing using Full-Search Block
Matching (FSBM) algorithm. The design employs parallel bank
architecture with minimum latency, maximum throughput, and full
hardware utilization. We use nine parallel processors in our
architecture and each controlled by a state machine. State machine
control implementation makes the design very simple and cost
effective. The design is implemented using VHDL and the
programming techniques we incorporated makes the design
completely programmable in the sense that the search ranges and the
block sizes can be varied to suit any given requirements. The design
can operate at frequencies up to 36 MHz and it can function in QCIF
and CIF video resolution at 1.46 MHz and 5.86 MHz, respectively.
Abstract: Recently, an enhanced hexagon-based search (EHS)
algorithm was proposed to speedup the original hexagon-based search
(HS) by exploiting the group-distortion information of some evaluated
points. In this paper, a second version of the EHS is proposed with a
new point-oriented inner search technique which can further speedup
the HS in both large and small motion environments. Experimental
results show that the enhanced hexagon-based search version-2
(EHS2) is faster than the HS up to 34% with negligible PSNR
degradation.