New VLSI Architecture for Motion Estimation Algorithm

This paper presents an efficient VLSI architecture design to achieve real time video processing using Full-Search Block Matching (FSBM) algorithm. The design employs parallel bank architecture with minimum latency, maximum throughput, and full hardware utilization. We use nine parallel processors in our architecture and each controlled by a state machine. State machine control implementation makes the design very simple and cost effective. The design is implemented using VHDL and the programming techniques we incorporated makes the design completely programmable in the sense that the search ranges and the block sizes can be varied to suit any given requirements. The design can operate at frequencies up to 36 MHz and it can function in QCIF and CIF video resolution at 1.46 MHz and 5.86 MHz, respectively.

Authors:

• V. S. K. Reddy
• S. Sengupta
• Y. M. Latha

Keywords:

• Video Coding
• Motion Estimation
• Full-Search
• Block-Matching
• VLSI Architecture.

References:

[1] Kuo-Liang Chung and Lung-Chun Chang, "A New Predictive Search
Area Approach for Fast Block Motion Estimation", IEEE Transactions
on Image Processing, vol. 12, no. 6, June 2003.
[2] Michael Brunig and Wolfgang Niehsen, "Fast Full-Search Block
Matching", IEEE Transactions on Circuits and Systems for Video
Technology, vol. 11, No. 2, Feb. 2001.
[3] J. R. Jain and A. K. Jain, "Displacement measurement and its application
in inter-frame image coding," IEEE Transactions on Communications,
vol. 29, pp. 799-808, Dec. 1981.
[4] Vasily G. Moshnyaga "A New Computationally Adaptive Formulation
of Block-Matching Motion Estimation" IEEE Transactions on Circuits
and Systems for Video Technology, vol. 11, no. 1, Jan. 2001.
[5] L.M. Po and W.C. Ma, "A novel four-step search algorithm for fast
motion estimation," IEEE Transactions on Circuits and Systems for
Video Tech., pp.313-317, June 1996.
[6] C. H. Hsieh and T. Lin, "VLSI architecture for block-matching motion
estimation algorithm", IEEE Transactions on Circuits and Systems for
Video Technology, vol. 2, pp. 169-175, June 1992
[7] T. Komarek, and P. Pirsch, "Array architectures for Block-Matching
Algorithms," IEEE Transactions on Circuits and Systems, vol. 36, pp.
1301-1308, Oct. 1989
[8] L. Do. K. Yun, "A Low-Power VLSI Architecture for Full-Search
Block-Matching Motion Estimation," IEEE Transactions on Circuits and
Systems for Video Technology, vol. 8, pp. 393-398, Aug 1998
[9] K.M. Yang and L. Wu, "A Family of VLSI Design for the motion
compensation Block-Matching Algorithm", IEEE Transactions on
Circuits and Systems, vol. 36, no. 10, pp. 1317-1325, Oct. 1989
[10] Seung Hyun Nam and Moon Key Lee, "Flexible VLSI architecture of
motion estimator for video image application," IEEE Transactions on
Circuits and Systems-II, vol. 43, no. 6, pp.467-470, June 1996
[11] Luc de Vos & M. Schobinger, " VLSI Architecture for a Flexible Block
Mathing Processor", IEEE transactions on Circuits and Systems for
Video Technology, vol. 5 no. 5 pp. 417-428. Oct. 1995.
[12] Rizzo D and Colavin O, "A video compression case study on a
reconfigurable VLIW architecture, Europe Conference and Exhibition in
Design, Automation and Test, P. 540 -546, Mar. 2002
[13] Gao R, Xu D and Bentley J.P, "Reconfigurable hardware
implementation of an improved parallel architecture for MPEG-4 motion
estimation in mobile applications", IEEE Transactions on Consumer
Electronics, Vol. 49, P.1383-1390, Nov. 2003
[14] H. Fujiwara et al. "An All-ASIC Implementation of Low Bit-Rate Video
Decoder," IEEE Transactions on Circuits and Systems, June 1992