Abstract: In this paper, the experimental design of using the
Taguchi method is employed to optimize the processing parameters in
the plasma arc surface hardening process. The processing parameters
evaluated are arc current, scanning velocity and carbon content of
steel. In addition, other significant effects such as the relation between
processing parameters are also investigated. An orthogonal array,
signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are
employed to investigate the effects of these processing parameters.
Through this study, not only the hardened depth increased and surface
roughness improved, but also the parameters that significantly affect
the hardening performance are identified. Experimental results are
provided to verify the effectiveness of this approach.
Abstract: The increasing influence of traffic on building
objects and people residing in them should be taken into account in
diagnosis and design. Users of buildings expect that vibrations
occurring in their environment, will not only lead to damage to the
building or its accelerated wear, but neither would affect the required
comfort in rooms designed to accommodate people. This article
describes the methods and principles useful in designing and building
diagnostics located near transportation routes, with particular
emphasis on the impact of traffic vibration on people in buildings. It
also describes the procedures used in obtaining information about the
parameters of vibrations in different cases of diagnostics and design.
A universal algorithm of procedure in diagnostics and design of
buildings taking into account assurance of human vibration comfort
of people residing in the these buildings was presented.
Abstract: Fast delay estimation methods, as opposed to
simulation techniques, are needed for incremental performance
driven layout synthesis. On-chip inductive effects are becoming
predominant in deep submicron interconnects due to increasing clock
speed and circuit complexity. Inductance causes noise in signal
waveforms, which can adversely affect the performance of the circuit
and signal integrity. Several approaches have been put forward which
consider the inductance for on-chip interconnect modelling. But for
even much higher frequency, of the order of few GHz, the shunt
dielectric lossy component has become comparable to that of other
electrical parameters for high speed VLSI design. In order to cope up
with this effect, on-chip interconnect has to be modelled as
distributed RLCG line. Elmore delay based methods, although
efficient, cannot accurately estimate the delay for RLCG interconnect
line. In this paper, an accurate analytical delay model has been
derived, based on first and second moments of RLCG
interconnection lines. The proposed model considers both the effect
of inductance and conductance matrices. We have performed the
simulation in 0.18μm technology node and an error of as low as less
as 5% has been achieved with the proposed model when compared to
SPICE. The importance of the conductance matrices in interconnect
modelling has also been discussed and it is shown that if G is
neglected for interconnect line modelling, then it will result an delay
error of as high as 6% when compared to SPICE.